Diminishing returns in single thread performance have forced a reevaluation of priorities in microprocessor design. Recent architectures have foregone deeper pipelining in favor of multiple cores per chip and multiple threads per core. The day approaches when processors with hundreds or thousands of cores are commonplace, but programming models for these manycore architectures lag far behind th...

The performance of an on-chip interconnection architecture used for communication between IP cores depends on the efficiency of its bus architecture. Any bus architecture having advantages of faster bus clock speed, extra data transfer cycle, improved bus width and throughput is highly desirable for a low cost, reduced time-to-market and efficient System-on-Chip (SoC). This paper presents a sur...

Besides performance and time to market, robustness and reliability are important design targets for modern Systemson-Chip (SoCs). Despite these features the power consumption must be as low as possible. To meet these design goals parallel, flexible, and adaptive architectures are required [1]. Today, dynamically reconfigurable FPGAs are well suited to form a parallel architecture because they i...

SOC test methodology in ultra deep submicron (UDSM) technology with reasonable test time and cost has begun to satisfy high quality and reliability of the product. A novel hierarchical test architecture using IEEE standard 1149.1, 1149.7 and 1500 compliant facilities is proposed for the purpose of supporting flexible test environment to ensure SOC test methodology. Each embedded core in a syste...

System-on-Chip (SoC) design is an integration of multi million transistors in a single chip for alleviating time to market and reduce the cost of the design. It uses the concept of design reuse to increase the productivity with reduction in time. In this paper we present a platform for a low cost SoC design using Open Core SoC design methodology. It offers flexible way of using reusable cores w...

Sparse matrix-vector multiplication (SpMV) is a central building block for scientific software and graph applications. Recently, heterogeneous processors composed of different types of cores attracted much attention because of their flexible core configuration and high energy efficiency. In this paper, we propose a compressed sparse row (CSR) format based SpMV algorithm utilizing both types of ...

Interactive theorem proving systems for mathematics require user interfaces which can present proof states in a human understandable way. Often the underlying calculi of interactive theorem proving systems are problematic for comprehensible presentations since they are not optimally suited for practical, human oriented reasoning in mathematical domains. The recently developed CORE theorem provi...

Magnetic nanoparticle systems can be divided into single-core nanoparticles (with only one magnetic core per particle) and magnetic multi-core nanoparticles (with several magnetic cores per particle). Here, we report multi-core nanoparticle synthesis based on a controlled precipitation process within a well-defined oil in water emulsion to trap the superparamagnetic iron oxide nanoparticles (SP...

Future wireless terminals will have to be multiband, multi-standard and able to execute multiple standards concurrently. In this paper we describe a flexible and programmable baseband platform for a large variety of mobile and WLAN standards. For the SDR platform architecture our primary design goal was to find the most flexible and easy-to-program solution within a specified power budget. The ...