Serial Flash Analog to Digital Converter (ADC) is a topology which uses only N number of comparators for N bit ADC. The said converter is developed and implemented in CMOS for 6 bit resolution. The simulation results are presented for TSMC 0.35 um CMOS technology

The present investigation proposes an efficient low power encoding scheme intended for a flash analog to digital converter. The designing of a thermometer code to binary code is one of the challenging issues in the design of a high speed low power flash ADC. An encoder circuit translates the thermometer code into the intermediate gray code to reduce the effects of bubble errors. The implementat...

PURPOSE To study the correlation between apparent diffusion coefficient (ADC) and pathology in patients with undefined breast lesion, to validate how accurately ADC is related to histology, and to define a threshold value of ADC to distinguish malignant from benign lesions. MATERIALS AND METHODS Seventy-eight patients (110 lesions) were referred for positive or dubious findings. Three-dimensi...

A 1Gsample/s 6-bit flash A/D converter with a combined chopping and averaging technique for reduced distortion in 0.18μm CMOS (May 2005) Nikolaos Stefanou Chair of Advisory Committee: Sameer Sonkusale Hard disk drive applications require a high Spurious Free Dynamic Range (SFDR), 6-bit Analog-to-Digital Converter (ADC) at conversion rates of 1GHz and beyond. This work proposes a robust, fault-t...

An 800MS/s CT ∆Σ ADC with 16MHz/32MHz bandwidths consumes 47.6mW from 1.8V and occupies 1mm in a 0.18μm CMOS process. The DR/SNR/SNDR for the two bandwidths are 75/67/65 dB and 64/57/57 dB respectively. Excess loop delay (ELD) of more than one cycle is compensated using a fast path outside the flash ADC. This and a low latency flash ADC and delay free DAC calibration result in the highest repor...

System-on-a-chip (SOC) requires integration of analog circuits and digital circuits on a single silicon chip to decrease cost, power dissipation, volume and radiant noise from the data bus on the printed circuit board (PCB). For these mixed-signal intergrated circuits, the standard digital CMOS technology is the best choice in view of cost, power dissipation and implementation convenience. The ...

Folding and interpolation ADC has been shown to be an important means of digitization of high BW signals at intermediate resolution. The objective of this paper is to design and identify the performance of the ADC. Flash ADC is one of the faster ways to convert any analog signal to a digital signal. It uses folding and interpolating techniques allow each comparator of the ADC to be reused sever...

A 3-bit, 2-V pipeline analog-to-digital converter has been designed using a modified flash architecture. The developed circuit blocks of the modified flash analog-todigital converter, operating at 135MHz, are a fully differential comparator, a digital-to-analog converter and a sample-and-hold amplifier. The design technique of the N-bit modified flash ADC requires only 2 1) comparators as compa...

VERITAS employs a 12m segmented mirror and pixellated photomultiplier tube camera to detect the brief pulse of Cherenkov radiation produced by the extensive air shower initiated by a cosmic high-energy gamma ray. The VERITAS data acquisition system consists of a 500 Mega-Sample-PerSecond custom-built flash ADC system, which samples the Cherenkov light pulse every 2 nanoseconds. The integrated c...