This paper presents a study of linearity in wideband CMOS low noise amplifiers (LNA) and its relationship to power consumption in context of Long Term Evolution (LTE) systems and its future developments. Using proposed figure of merit (FoM) to compare 35 state-of-the-art LNA circuits published over the last decade, the paper explores a dependence between amplifier performance (i.e., combined li...

Abstract New paths to increase the sensing performance of plasmonic sensors have been reported in recent years. There are several methodologies achieve such purpose, namely by optimizing nanostructure, nanomaterial and even platform. Recently use nanoparticles over thin films shown sensitivity enhancement, when compared a bare film. Nevertheless, combination between NP film has not studied. In ...

Plasmonic sensors have attracted intensive attention due to their high sensitivity. However, intrinsic metallic loss, plasmonic usually a large full width at half maximum (FWHM) that limits the wavelength resolution. In this paper, we numerically investigate and propose dielectric grating-assisted device, leveraging bound states in continuum (BIC) effect suppress FWHM of resonance. We initiate ...

This paper presents the first measured cyclic-coupled ring oscillator (CCRO) time-to-digital converter (TDC). The CCRO realizes a robust true time-domain delay interpolation with sub-gate-delay resolution. architecture employs real-time quantization to reduce conversion time and hence maximize bandwidth. Furthermore, phase progression is encoded bubble error suppression logic, thereby building ...

A sigma delta modulator incorporating a linear phase integrator instead of a conventional voltage-domain integrator is described. The architecture allows achieving a quasi-second order noise shaping by using a passive SC low-pass filter in the first stage. Simulation results demonstrate that the circuit can operate with sampling frequencies of hundred of MHz while obtaining a figure of merit (F...

We demonstrate an improvement by more than 1 order of magnitude of the figure of merit (FoM) of plasmonic nanoparticle sensors by means of the diffractive coupling of localized surface plasmon resonances. The coupling in arrays of nanoparticles leads to Fano resonances with narrow line widths known as surface lattice resonances, which are very suitable for the sensitive detection of small chang...

Word spotting is a widely known subject in continuous speech recognition and the traditional approaches use either hidden Markov models (HMM) or Gaussian mixture models (GMM). In this paper, we propose a different approach based on language independent phoneme modeling. The proposed system is speaker and vocabulary independent, and it is easy to implement. An equal error rate (EER) of 3.34% and...

A differential Colpitts oscillator using AlN MEMS CMR designed in 0.13 um CMOS is presented in this work. The oscillator operates at 1.16 GHz, with a total power consumption of 4.2 mW at 1 V supply. It achieves a phase noise of -143.6 dBc/Hz, 173.3 dBc/Hz at 100 kHz and 1 MHz offset frequency respectively with a figure of merit (FOM) of 228.3 dB. Current-based temperature compensation was emplo...

In this paper, we present a low power 12 bit 5 MSPS, successive approximation converter architecture using pipeline technique. The converter consumes 4 mW at the Nyquist rate input with 1.8 V power supply. By combination of pipeline and successive architecture, the entire circuit, simulated at the transistor level in a 0.18 μ CMOS process, achieves a FoM (Figure of Merit) of 0.19 pJ/conversion.

In a classical PLL, the phase detector (PD) and charge pump (CP) noise is multiplied by N, when referred to the VCO output, due to the divide-by-N in the feedback path. It often dominates the in-band phase noise and limits the achievable PLL jitter•power Figure-Of-Merit (FOM). A sub-sampling PLL uses a PD that sub-samples the high frequency VCO output with the reference clock. The PD and CP noi...