The paper describes a new approach of a flexible run-time system for handling dynamic function reconfiguration in fme-grain Virtex FPGAs, whereas the fulfillment of given real-time constraints are central. Moreover, the detailed evaluation and measurement of the power consumption situation during this dynamic reconfiguration process is essential for realistically quantifying the power loss of f...

This paper shows an area-efficient and high-speed architecture for IPv6 lookup using a parallel index generation unit (IGU). To reduce the size of memory in the IGU, we use a liner transformation and a row-shift decomposition. Also, this paper shows a design method for the parallel IGU. A single memory realization requires O(2) memory size, where n denotes the length of prefix, while the IGU re...

101 The Design of an SRAM-Based Field-Programmable Gate Array, Part II: Circuit Design and Layout Paul Chow, Soon Ong Seo, Jonathan Rose, Kevin Chung, Gerard P aez-Monz on and Immanuel Rahardja Abstract|Field-Programmable Gate Arrays (FPGAs) are now widely used for the implementation of digital systems and many commercial architectures are available. Although the literature and data books conta...

The development and automatic generation of Built-In Self-Test (BIST) configurations for Atmel AT40K series Field Programmable Gate Arrays (FPGAs) are described. These BIST configurations completely test the programmable logic and routing resources in the core of the FPGA along with the dedicated Random Access Memories (RAMs) dispersed within the array. The BIST configurations are generated usi...

This paper describes a novel Field Programmable Gate Array (FPGA) logic synthesis technique which determines if a logic function can be implemented in a given programmable circuit and describes how this problem can be formalized and solved using Quantified Boolean Satisfiability. This technique is general enough to be applied to any type of logic function and programmable circuit; thus, it has ...

The current ultrasound therapy machines are implementing continuous waveform, which in fact, is not an optimum technique for therapy treatment process. Apparently, pulse waveform appearing as a more effectively way of signal generation in terms of its power consumption, low cost hardware and short timing used. In order to overcome these drawbacks of conventional therapy machines, we proposed a ...

In this paper, a new controllable V-shape multiscroll attractor is presented, where a variety of symmetrical and unsymmetrical attractors with a variable number of scrolls can be controlled using new staircase nonlinear function and the parameters of the system. This attractor can be used to generate random signals with a variety of symbol distribution. Digital implementation of the proposed ge...

This paper describes an evolvable image filter which is completely implemented in a field programmable gate array. The proposed system is able to evolve an image filter in a few seconds if corrupted and original images are supplied by user. The architecture is generic and can easily be modified to realize other evolvable systems. COMBO6 card with Xilinx Virtex xc2v3000 FPGA is used as a target ...

A novel hardware based design for the Internet Protocol version 6 (IPv6) router using Field Programmable Gate Array (FPGA) has been proposed. The router is implemented in Xilinx XCV1000BG560 FPGA, works at a clock frequency of 16 MHz with an average throughput of 980 Mbps.

This paper describes the attributes and goals for a radiation-hard and high-reliability Field Programmable Gate Array (FPGA). The first Qualified Manufacturer List (QML) radiation-hardened antifuse FPGA, RH1280, is characterized. Its total dose and Single Event Effects (SEEs) are tested and the results are reported. Trade-offs and limitations in Single Event Upset (SEU) hardening are also discu...