This paper deals with reconfigurable back-to-back converter topology and control orders in Wind Energy Conversion Systems (WECS). A typical WECS with Doubly Fed Induction Generator (DFIG) in balanced conditions is concerned. Based on the classical topology, a fault tolerant converter without any redundancy has been studied. The presented fault tolerant topology allows a “five-leg” structure wit...

Exploiting recent advances in quantum trapped-ion technologies, we propose a scalable, fault-tolerant quantum computing architecture that overcomes the fundamental challenges of building a full-scale quantum computer and leaves the fabrication a daunting but primarily an engineering concern. Using a hierarchical array-based design and a quantum teleportation communication protocol, we are able ...

There are quantum algorithms that can efficiently simulate quantum physics, factor large numbers and estimate integrals. As a result, quantum computers can solve otherwise intractable computational problems. One of the main problems of experimental quantum computing is to preserve fragile quantum states in the presence of errors. It is known that if the needed elementary operations (gates) can ...

A permanent physical fault in communication lines usually leads to a failure. The feasibility of evolution of a self organized communication is studied in this paper to defeat this problem. In this case a communication protocol may emerge between blocks and also can adapt itself to environmental changes like physical faults and defects. In spite of faults, blocks may continue to function since ...

Defect rate in Nanoelectronics is much higher than conventional CMOS circuits. Hardware redundancy can be a suitable solution for fault tolerance in nano level. A voter circuit is a part of a redundancy based fault tolerant system that enables a system to continue operating properly in the event of one or more faults within its components. Robustness of the voter circuit defines the reliability...

We present an algorithm for efficiently approximating of qubit unitaries over gate sets derived from totally definite quaternion algebras. It achieves ε-approximations using circuits of length O(log(1/ε)), which is asymptotically optimal. The algorithm achieves the same quality of approximation as previously-known algorithms for Clifford+T [arXiv:1212.6253], V-basis [arXiv:1303.1411] and Cliffo...

We report high-fidelity laser-beam-induced quantum logic gates on magnetic-field-insensitive qubits comprised of hyperfine states in ^{9}Be^{+} ions with a memory coherence time of more than 1 s. We demonstrate single-qubit gates with an error per gate of 3.8(1)×10^{-5}. By creating a Bell state with a deterministic two-qubit gate, we deduce a gate error of 8(4)×10^{-4}. We characterize the err...

Testable fault tolerant system design has become vital for many safety critical applications. On the other hand, reversible logic is gaining interest in the recent past due to its less heat dissipating characteristics. Any Boolean logic function can be implemented using reversible gates. This paper proposes a technique to convert any reversible logic gate to a testable gate that is also reversi...

Today, the use of CMOS technology for the manufacture of electronic ICs has faced many limitations. Many alternatives to CMOS technology are offered and made every day. Quantum-dot cellular automata (QCA) is one of the most widely used. QCA gates and circuits have many advantages including small size, low power consumption and high speed. On the other hand, using special digital gates called re...