This paper presents a path-based fault-injection approach to increase the eeciency of computer system dependability evaluation. Our approach utilizes knowledge about the execution path to ensure that injected faults are activated. The control ow associated with each path is analyzed to determine the faults that would be activated by that path. By selecting a set of paths that covers a signiican...

— pin-level fault injection, heavy-ion radiation, and electromagnetic interference (EMI) — and their use in the validation of MARS, a faulttolerant distributed real-time system. The objectives of this study are: (i) to validate the fault-tolerance features of the MARS system, and (ii) to gain a better understanding of the features and impact of the three fault injection techniques. Coverage mea...

This paper addresses the issue of characterizing the respective impact of fault injection techniques. Three physical techniques and one software-implemented technique that have been used to assess the fault tolerance features of the MARS faulttolerant distributed real-time system are compared and analyzed. After a short summary of the fault tolerance features of the MARS architecture and especi...

Full chip statistical fault injection has been performed on a hardware emulated POWER6 platform. These results were validated against proton beam injection results. The fault isolation, error recovery and error logging capabilities of the POWER6 enabled measurement of the architectural derating factors. The proportion of errors as well as derating factors matched well between the simulated and ...

system has very much importance because it will increase performance and accuracy. The fault injection method is used to find out the fault tolerance of a system. This method is valuable and attractive. In this paper fast FPGA based fault injector for memory unit is introduced. In previous FPGA based fault injection methods the response according to the fault injection is send to the observatio...

A silicon independent C-Based model of the TTP/C protocol was implemented within the EU-founded project FIT. The C-based model is integrated in the C-Sim simulation environment. The main objective of this work is to verify whether the simulation model of the TTP/C protocol behaves in the presence of faults in the same way as the existing hardware prototype implementation. Thus, the experimental...

This note1 describes a software-implemented Fault Injection system (Fig. 1) suited to be used with embedded microprocessor-based boards and based on some features available in the most recent microprocessors and microcontrollers. Although these features were originally introduced to easy code development and debugging, they are very well suited for supporting the implementation of efficient and...

This thesis deals with the problem of validating and estimating the effectiveness of error handling mechanisms in computer systems. The main contribution is an assessment of the effectiveness and usefulness of several physical fault injection techniques. The assessment is based on fault injection experiments conducted on the fault-tolerant, distributed, real-time system MARS and the Thor microp...

This paper presents an overview about FPGA based fault injection tools which are developed by using the instrumentation technique or modification in the original code. The fault injection technique is used to evaluate dependability parameters of computer based embedded systems or safety critical systems, by injecting faults in a system. An observation on the behaviour or of the response for bot...

A fault is a defect in a program, usually difficult to pinpoint .A faults may occur at single points or distributed points. In software testing, fault injection is a technique of introducing faults into the code for improving the coverage and usually used with stress testing for robustness of the developed software. When the fault-tolerance mechanisms detect an error, they may initiate several ...