ESD/latchup are often two contradicting variables during IC reliability development. Trade-off between the two must be properly adjusted to realize ESD/latchup robustness of IC products. A case study on SERIAL Input/Output (I/ O) IC’s is reported here to reveal this ESD/latchup optimization issue. SERIAL I/O IC features a special clamping property to wake up PC’s during system standby situation...

ESD structures have inevitable parasitic impacts on circuit performance. This paper reports results of an investigation into ESD-induced circuit performance degradation in RFICs including clock corruption, reduced slew rate, narrowed bandwidth, and noise generation. Performance degradation of ~80%, ~30% & ~5% were observed in clock, Op Amp and LNA circuits studied, which were recovered substant...

the multivariate exponentially weighted moving average (mewma) control chart is one of the best statistical control chart that are usually used to detect simultaneous small deviations on the mean of more than one cross-correlated quality characteristics. the economic design of mewma control charts involves solving a combinatorial optimization model that is composed of a nonlinear cost function ...

A Cochrane systematic review showed that Early Supported Discharge (ESD) following a stroke is both a safe and cost-effective alternative to continued in-patient management. Currently it is unclear whether the health and cost benefits established in the research literature still apply when ESD services are implemented in practice. Our study aims to evaluate the implementation of stroke ESD acro...

A substrate-triggered technique is proposed to improve ESD protection efficiency of the stacked-NMOS device in the mixed-voltage I/O circuit. The substrate-triggered technique can further lower the trigger voltage of the stacked-NMOS device to ensure effective ESD protection for the mixed-voltage I/O circuit. The proposed ESD protection circuit with the substrate-triggered technique for 2.5V/3....

A dynamic gate floating design is proposed to improve ESD robustness of the CMOS output buffers with small drive capability. By using this novel design, the human-body-model (machine-model) ESD failure threshold of a 2-mA CMOS output buffer has been practically improved from 1 KV (100 V) to greater than 8 KV (1500 V) in a 0.35m CMOS process.

SUMMARY An impedance-isolation technique is proposed for on-chip ESD protection design for radio-frequency (RF) integrated circuits (ICs), which has been successfully verified in a 0.25-μm CMOS process with thick top-layer metal. With the resonance of LC-tank at the operating frequency of the RF circuit, the impedance (especially, the parasitic ca-pacitance) of the ESD protection devices can be...

Electro Static Discharge (ESD) analysis is of vital importance during the design of large-scale integrated circuits, since it gives insight in how well the interconnect can handle unintended peak charges. Due to the increasing amount of interconnect and metal layers, ESD analysis may become very time consuming or even unfeasible. We propose an algorithm for the reduction of large resistor netwo...

A new design on the electrostatic discharge (ESD) protection scheme for CMOS IC operating in power-down-mode condition is proposed. By adding a VDD_ESD bus line and diodes, the new proposed ESD protection scheme can block the leakage current from I/O pin to VDD power line to avoid malfunction during power-down-mode operating condition. During normal circuit operating condition, the new proposed...

Verification of electrostatic discharge (ESD) design rules has grown in volume and complexity as IC designs have become more complex and added significantly more power domains. With each additional power domain, verification of the signals that cross these domains becomes more difficult (particularly in the identification of inadvertent paths), as well as the check of interactions between circu...