A gate-controlled metal-semiconductor barrier modulation and its effect on carrier transport were investigated in two-dimensional (2D) transition metal dichalcogenide (TMDC) field effect transistors (FETs). A strong photoresponse was observed in both unipolar MoS2 and ambipolar WSe2 FETs (i) at the high drain voltage due to a high electric field along the channel for separating photo-excited ch...

This paper investigates the effect of gate electrode work function in 30 nm gate length conventional and junctionless FinFETs using technology computer-aided design (TCAD) simulations. DC parameters, threshold voltage (vt), drive current (Ion) and output resistance (Ro), and RF parameters, unity gain cutoff frequency (ft), non-quasi static (NQS) delay and input impedance (Z11) are investigated....

Abstract Multi-gate MOSFETs are considered for realizing ultra-low-power circuits due to their superior channel control capability and short effect (SCE) resistance. To achieve this goal, it is necessary establish a suitable compact device circuit model them. However, current research focuses more on single-material multi-gate MOSFET, there no report dual-material logic gates. In work, we devel...

A new Row-by-Row Dynamic Source-line Voltage control (RRDSV) scheme is proposed to reduce the active leakage as well as the stand-by leakage in SRAM. By dynamically controlling the source-line voltage of cells row by row, the cell leakage through inactive cells can be reduced by two orders of magnitude. Moreover, the bit-line leakage through pass transistors can be completely cut off. This leak...

The novel characteristics of a new type of MOSFET, the hetero-material gate field-effect transistor (HMGFET), are explored theoretically and compared with those of the compatible MOSFET. Two conceptual processes for realizing the HMG structure are proposed for integration into the existing silicon technology. The two-dimensional (2-D) numerical simulations reveal that the HMGFET demonstrates ex...

Amount of power consumption is one of the important measures of performance of an integrated circuit. CMOS is the latest technology which is in use till date. This paper gives an overview of the power dissipation occurring in CMOS circuit. The paper then describes the advantages and limitations of power optimization techniques of CMOS. As we go deeper into the nanometer scale, MOS transistors f...

In this paper, we have performed the scaling of asymmetric junctionless (JL) SOI nanowire (NW) FET at 10 nm gate length (LG). To study device electrical performance various DC metrics like SS, DIBL, ION/IOFF ratio are discussed. Even 5 nm, has good properties with subthreshold swing (SS) = ~64 mV/dec, drain induced barrier lowering (DIBL) ~45 mV/V, and switching (ION/IOFF) ~106 shows a higher l...

This paper presents a closed-form compact model for the undoped double-gate (DG) MOSFET under symmetrical operation. This charge-based model aims at giving a comprehensive understanding of the device from the circuit design point of view. Both static and dynamic models are derived in terms of simple analytic relationships based on our new explicit formulation of the mobile charge density. Our a...

We present a modeling scheme for simulating ballistic hole transport in thin-body fully depleted silicon-on-insulator pMOSFETs. The scheme includes all of the quantum effects associated with hole confinement and also accounts for valence band nonparabolicity approximately. This simulator is used to examine the effects of hole quantization on device performance by simulating a thin (1.5-nm) and ...

We present an analytical and continuous dc model for undoped cylindrical surrounding double-gate (CSDG) MOSFETs for which the drain current and subthreshold model is written as an explicit function of the applied voltages for the wireless telecommunication systems to operate at the microwave frequency regime of the spectrum. The model is based on a unified charge control model developed for thi...