Abstract—A compact dual-band power divider for GSM/DCS applications is proposed in this letter. Novel planar artificial transmission lines are applied to miniaturize the power divider and achieve wideband response. The proposed dual-band power divider is about 37% of conventional one. The design principle, simulated and measured results are all discussed. The measured results show that good per...

The implementation of a programmable high speed divider for a CMOS Frequency Synthesizer, using 0.35 μm CMOS technology, is described. The Frequency Synthesizer is part of a RF transceiver to work in the 2.4 GHz ISM (Industrial, Scientific and Medicine) band. The programmable divider employs: a divide-by-32/33 dual-modulus prescaler composed by a divide-by-4/5 synchronous counter, using the Ext...

The objective of this project is to develop a Programmable Frequency divider design for multi GHz PLL System implementation on FPGA using VHDL (hardware description language). The frequency divider architecture features 6 parallel divider chains, each one of them implementing a single division ratio. The desired frequency division ratio is then selected using the four control bits of an output ...

This paper proposes an idea to modify the conventional Wilkinson power dividers to have physically spaced output ports. The well-known internal resistor of Wilkinson power divider is now connected to output ports by two additional transmission lines to create a triangular shape power divider. Several modified power dividers are designed at frequency of 1.0 GHz and one of them is fabricated and ...

An effort is pursued by several European National Measurement Institutes to lower the uncertainties in calibration of UHV measuring systems for lighting impulse. To this end, several reference dividers are investigated as regards their accuracy both for amplitude and for time parameters. At SP RISE Research Institutes of Sweden, a 500 kV resistive reference divider has been in use since 2000. A...

We present a scalable high-speed divide-by-N frequency divider using only basic digital CMOS circuits. The divider achieves high-speed operation using a novel parallel counter and a pipelined architecture. The parallel counter is based on a state look-ahead component in conjunction with an internal pipeline structure in order to simultaneously trigger all state value updates without a rippling ...

This paper presents a monolithically integrated broadband lumped-element Wilkinson power divider centered at 20 GHz, which was designed and fabricated to uniformly distribute power to arrays of Josephson junctions (JJs) for superconducting voltage standards. This solution achieves a fourfold decrease in chip area, and a twofold increase in bandwidth (BW) when compared to the previous narrowband...

Processing floating point division generally consists of SRT recurrence, quotient conversion, rounding, and normalization steps. In the rounding step, a high speed adder is required for increment operation, increasing the overall execution time. In this paper, a floating point divider performing quotient conversion and rounding in parallel is presented by analyzing the operational characteristi...

─ In this paper, a novel microstrip power divider with a new technique for nth harmonic suppression is presented. This technique is based on using front coupled tapered compact microstrip resonant cell (FCTCMRC) that inserted into a quarter-wavelength transmission line of the conventional Wilkinson power divider. This cell is used to obtain high harmonic suppression. The proposed power divider ...