Presented is a 0.9 V rail-to-rail constant gm CMOS amplifier input stage consisting of complementary differential pairs and a gm control circuit. The gm control circuit eliminates the gm dead zone, which occurs in the conventional rail-to-rail amplifier with ultra-low supply voltages. The proposed amplifier input stage has a constant gm that varies by +2.3% for rail-to-rail input common-mode le...

A simple numerical procedure has been implemented as a Matlab script to allow straightforward design of high speed, resistor loaded, differential amplifiers in modern CMOS processes. The amplifier, shown in Figure 1, exhibits device characteristics that dramatically depart from traditional square law characterisitics making designs based on hand calculations grossly inaccurate. The analytical f...

L-band SiGe HBT differential amplifiers with multiple bandpass or bandstop performance is presented. It incorporates stacked parallel-resonant circuits into the design of the output load of the differential amplifier to achieve multiple bandpass performance. On the other hand, the stacked parallel-resonant circuits are used between emitters of the differential transistor-pair to achieve multipl...

Simulation of phase sensitive amplifier (PSA) of differential phase shift keying (DPSK) data signal in dual pump is presented. The PSA is designed and simulated using OptiSystem software. A dual pump PSA based on cascaded fiber optic parametric amplifier (FOPA) of 80Gbit/s DPSK data signal is investigated in detail on its gain and noise figure. Results show that PSA has higher gain and lower no...

In this paper we present a three-stage fully differential operational amplifier in 120nm digital CMOS. To reach high gain gain-boosted cascodes in the first stage are used. The gain-boost amplifiers are realized as two-stage amplifiers with self cascodes. A DC gain of 108dB and an unity-gain frequency of 1.06GHz are achieved at 1.2V supply. The operational amplifier is appropriate for supply vo...

This CMOS voltage sense amplifier or comparator is designed by adding dual input single output differential amplifier which is added in place of back-to-back inverter in the latch stage. This method is used to completely remove the input noise present in the circuit. Using this dual input single output differential amplifier the analog-to-digital conversions with high speed, lower power dissipa...

in this paper first we try to analysis the behavior ofthe soas in the optical networks and then have proposed anumerical simple model to simulate the behavior of thesemiconductor optical amplifiers. after that by employing thismodel as inline amplifier for a dwdm optical system, we havesimulated the transmission of 10 channels with bit rate 10 gb/sup to distance 3970 km with rz-dpsk modulation ...

This paper presents a fixed gain high output power amplifier with performance determined by using on-wafer measurement. The amplifier is fully differential based on inductive load and resistive degeneration which is designed using a 0.18 μm SiGe BiCMOS process. The amplifier achieves power gain of 7.2 dB, 3-dB bandwidth of 2.06 GHz, operating frequency of 12 GHz, power consumption of 12 mW usin...

In this paper, a 10-Gb/s inductorless CMOS receiver front end is presented, including a transimpedance amplifier and a limiting amplifier. The transimpedance amplifier incorporates Regulated Cascode (RGC), active-inductor peaking, and intersecting active feedback circuits to achieve a transimpedance gain of 56 dB and a bandwidth of 8.27 GHz with a power dissipation of 35 mW. The limiting amplif...