This paper describes the implementation of a SPI-programmable clock delay chip based on a Delay Locked Loop (DLL) in order to shift the phase of the LHC clock (25 ns) in steps of 1ns, with less than 5 ps jitter and 23 ps of DNL. The delay lines will be integrated into ICECAL, the LHCb calorimeter front-end analog signal processing ASIC in the near future. The stringent noise requirements on the...

Substrate noise is the major source of performance limitation in mixed-signal integrated circuits. This paper studies substrate noise effects on the performance of delay-locked loops (DLLs). Due to their robust noise performance, the delay-lockedloops are widely used as clock generators of microprocessors. Although exploiting advanced circuit techniques reduces the timing jitter induced by the ...

In a coherent RAKE receiver the complex channel coee-cient estimate can be used to attain the phase coherency in DLL and the eeect of data modulation can be removed via decision feedback. The resulting algorithms are called quasi-coherent delay-locked loops (QCDLL). The performance of four variations for QCDLLs based on lead-lag phase-locked loops has been analyzed by computer simulations. All ...

A four-phase all-digital delay-locked loop (ADDLL) with a de-skew circuit for NAND Flash high-speed interfaces is proposed. The proposed adopts fall-edge-judgment phase adjuster and three-stage digitally controlled delay line to align the system input clock 0∘ output of DLL over wide frequency range, thus solving offset caused by skew. parallel-cascade configuration solve variable alignment pro...

In this paper, for the wireless network, wearable device, and Internet of Things (IoT) markets, a delay-locked loop (DLL) is used to implement accurate multiplication reference clock frequency various applications through an edge combiner (EC). A simpler structure more sensitive process, voltage, temperature (PVT), so DLL complements itself quickly in feedback system improves stability final ou...

In this paper, we analyze a noise-to-jitter transfer function on DLL (Delay Locked Loop) considering power supply noise effects on PDN (Power Distribution Network). Noise-tojitter transfer function of DLL circuit can be estimated by using single-tone power supply noise analysis. Noise transfer function through the PDN can be obtained from transfer impedance of hierarchical PDN using TLM (Transm...

Mitigating multipath of cellular long-term evolution (LTE) signals for robust positioning in urban environments is considered. A computationally-efficient receiver, which uses a phase-locked loop (PLL)-aided delay-locked loop (DLL) to track the received LTE signals is presented. The DLL uses an orthogonal frequency division multiplexing (OFDM)–based discriminator function to estimate and track ...

In this paper, we present a novel approach to comprehensively verify timing sensitive blocks, specifically Delay Lines and Delay Locked Loops by modelling transient behavior into the RTL. This paper focuses on reduction of simulation time and increase in design turnaround time. Information gathered from a small set of spice simulations is modelled into a Verilog based environment, which gives s...

This paper presents analyses and experimental results on the jitter transfer of delay-locked loops (DLLs). Through a -domain model, we show that in a widely used DLL configuration, jitter peaking always exists and high-frequency jitter does not get attenuated as previous analyses suggest. This is true even in a firstorder DLL and an overdamped second-order DLL. The amount of jitter peaking is s...

The synchronization of the received pseudorandom (PRN) code and the local generated replica is fundamental to compute user position in Global Navigation Satellite System (GNSS) receivers. The more accurate correlation output and Delay Locked Loop (DLL) code tracking error are described in this paper from the hardware receiver point of view. Estimation is based on the number of samples per code ...