In this paper, we consider the problems of identiication of delay-fault-sensitive components in a pipelined combinational circuit, and of circuit modiication to improve the circuit's tolerance of delay faults. The results assume purely combinational logic, and xed gate delays calculated under oating delay mode.

Delay of VLSI circuit components can be controlled by varying their sizes. In other words, performance of VLSI circuits can be optimized by changing the sizes of the circuit components. In this paper, we define a special type of geometric program called unary geometric program. We show that under the Elmore delay model, several commonly used formulations of the circuit component sizing problem ...

This paper proposes a fast estimation method for energy and latency of QDI (quasi delay-insensitive) asynchronous circuits. The energy and latency results can be combined into an Et n metric for allowing comparison between different asynchronous implementations. Furthermore, each implementation can be transformed and new values of energy and latency can be quickly and easily recalculated. In th...

in this paper, a new structure possessing the advantages of low-power consumption, less hardware and high-speed is proposed for fuzzy controller. the maximum output delay for general fuzzy logic controllers (flc) is about 86 ns corresponding to 11.63 mflips (fuzzy logic inference per second) while this amount of the delay in the designed fuzzy controller becomes 52ns that corresponds to 19.23 m...

This paper presents a variable delay line DLL circuit implemented in a 0.8 m CMOS technology. A phase detector and two charge pump circuits calibrate the delay per stage of the delay line using push-pull type clock synchronization scheme. The delay line can be programmed 6 to 18 stages. The DLL circuit is capable of reducing clock skew from 1-3ns to below 500ps for clock frequencies from 50Mhz ...

Abstract In this paper we propose a new compact static delay model for latch-based CMOS Threshold logic gates. The particular effects captured by the model are: the dependency of the delay on threshold (data) values and the dependency of the delay vs. capacitive loading. The model parameters were extracted from several Threshold logic gate setups and the delay predicted by the model for a compu...

This study introduces a reversible optical fulladder. Also optical NOT and NOR gates are implemented through Electro-Absorption-Modulator / Photo Detector (EAM/PD) pairs, were utilized for fulfilling reversible R gate. Then, reversible fulladder was designed based on the proposed reversible optical R gate. The operation of the suggested fulladder was simulated using Optispice and it was fou...