This paper presents a test technique that employs two different supply voltages for the same Iddq pattern. The results of the two measurements are subtracted in order to eliminate the inherent subthreshold leakage. Summary of the experiment carried out on “System on a Chip” (SOC) device build in 0.35μ technology is also shown. These experiments proved that the method is effective in detecting f...

High leakage current in deep sub-micron regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, leakage control and reduction are very important, especially for low power applications. The reduction in leakage current has to be achieved using both process and circuit level techn...

tioned the ability to carry out effective currentbased testing (IDDX) for deep-micron VLSIs.1-5 Yet, current-based test methods for such devices are more relevant than ever. The probability of a defect occurring increases exponentially as its size decreases. As the technology scales, even smaller defects may become potential threats to yield. Furthermore, ensuring gate oxide quality and reliabi...

One of the most notable features of nanometer scale CMOS technology is the increasing magnitude of variability of the key parameters affecting performance of integrated circuits [1]. Although scaling made controlling extrinsic variability more complex, nonetheless, the most profound reason for the future increase in parameter variability is that the technology is approaching the regime of funda...

Damascene approaches are widely used for creating microelectronic interconnects. Successful implementation of the process is reliant upon the deposition of a refractory metal or metal nitride liner coating. It functions as a diffusion barrier layer to suppress transport of subsequently deposited interconnect metals into the surrounding dielectric. The development of vapor-phase processes for th...

System on–chip design in deep submicron technology interconnects plays an important role in overall performance of the chip. Digital circuits consists of a number of interconnected logic gates which together perform a logic operation with more input signals. When an input signal changes the change will propagates via the gates to the circuit generating energy transition The signal transition ca...

In this work, IDDQ current for the deep submicron VLSI in year 2011 is estimated with a statistical approach according to the International Technology Roadmap for Semiconductors 1999 Edition considering process variations and different input vectors. The estimated results show that the standard deviation of the IDDQ current is proportional to the square root of the circuit size and the IDDQ cur...

The Scaling of microchip technologies, from micron to submicron and now to deep sub-micron (DSM) range, has enabled large scale systems-on-chip (SoC). In future deep submicron (DSM) designs, the interconnect effect will definitely dominate performance. Network-on-Chip (NoC) has become a promising solution to bus-based communication infrastructure limitations. NoC designs usually targets Applica...

This paper presents a detailed study of the nonuniform bipolar conduction phenomenon under electrostatic discharge (ESD) events in single-finger NMOS transistors and analyzes its implications for the design of ESD protection for deep-submicron CMOS technologies. It is shown that the uniformity of the bipolar current distribution under ESD conditions is severely degraded depending on device fing...