This contribution focuses on the optimization of matching-based motion estimation algorithms widely used for video coding standards using an Altera custom instruction-based paradigm and a combination of synchronous dynamic random access memory (SDRAM) with on-chip memory in Nios II processors. A complete profile of the algorithms is achieved before the optimization, which locates code leaks, an...

This paper describes an approach for adaptive dynamic instruction set extension, tuning embedded processors to specific applications which are going to be executed in their life-time. These new instructions are generated after production. The processor has two modes: training mode and normal mode. Training mode can be done offline or online. The applicationspecific instructions are extracted fr...

The design of software countermeasures against active and passive adversaries is a challenging problem that has been addressed by many authors in recent years. proposed solutions adopt theoretical foundation (such as leakage model) but often do not offer concrete reference implementations to validate the foundation. Contributing experimental dimension this body work, we propose customized proce...

This paper presents a new merit function for custom instruction selection phase of the design flow of application-specific instruction-set processors (ASIPs) in the presence of an area budget constraint. In contrast to nearly all of the previously proposed approaches where ratio of the ASIP speed to layout area is used as a merit function to select the candidate custom instructions (CIs), we sh...

As custom multicore architectures become more and more common for DSP applications, instruction selection and scheduling for such applications and architectures become important topics. In this paper, we explore the effects of defining the problem of finding an optimal instruction selection and scheduling as a constraint satisfaction problem (CSP). We incorporate methods based on sub-graph isom...

The Malleable Architecture Generator (MARGE) is a tool set that translates high-level parallel C to connguration bit streams for eld-programmable logic based computing systems. MARGE creates an application-speciic instruction set and generates the custom hardware components required to perform exactly those computations speciied by the C program. In contrast to traditional xed-instruction proce...

Application Speciic Instruction set Processors (ASIPs) are eld or mask programmable processors of which the architecture and instruction set are opti-mised to a speciic application domain. ASIPs ooer a high degree of exibility and are therefore increasingly being used in competitive markets like telecommunications. However, adequate CAD techniques for the design and programming of ASIPs are mis...

This paper describes CodeSyn, a retargetable microcode synthesis system for applicationspecific instruction-set processors (ASIP). With respect to commercial or publicly available compilers, the main strengths of the CodeSyn system are in three main areas: ● Flexible and powerful instruction-set specification style which supports quick retargeting to new processors. . A pattern matching algorit...

Application-specific processor design is a promising approach for meeting the performance and cost goals of a system. Application-specific integrated processors (ASIP’s) are especially promising for embedded systems (e.g., automobile control systems, avionics, cellular phones, etc.) where a small increase in performance and decrease in cost can have a large impact on a product’s viability. Suth...

This paper presents the MANTRA I machine, an SIMD neuro-computer based on a square systolic array of dedicated processing elements (PEs). A VLSI custom chip, called GENES IV containing 2 2 PEs is at the heart of the system. This machine implements suucient instruction and data ows to keep the array's utilization rate close to 100 %.