We designed a compact, high-speed, and low-power bank-type 12-port register file test chip for highly-parallel processors in 0.35μm CMOS technology. In this full-custom test chip design, 72% smaller area, 25% shorter access cycle time, and 62% lower power consumption are achieved in comparison to the conventional 12-port-cell-based register file.

The possibility of using window comparators for onchip (and potentially on-line) response evaluation of analogue circuits is investigated. No additional analogue test inputs are required and the additional circuitry can be realised either by means of standard digital gates taken from an available library or by full custom designed gates to obtain an observation window tailored to the applicatio...

This paper summarizes the content and application of the SEED2002 project. SEED2002 is a university/industry collaboration to enhance and reform the education in the field of semi-custom/full-custom ASIC design at the universities of Mannheim, Heidelberg and Kaiserslautern, Germany. With this project Cadence Design Systems enables us to teach leading-edge ASIC design using their most innovative...

1 Structural Engineering Department, Federal University of Juiz de Fora, Juiz de Fora, MG 36036-330, Brazil 2 Institute of Modeling and Computation, Hamburg University of Technology, 21073 Hamburg, Germany 3 Department of Mechanics, Slovak Academy of Sciences, 845 03 Bratislava, Slovakia 4 CICC—Research Center in Construction Sciences, Department of Civil Engineering, University of Coimbra, 303...