We demonstrate large-scale (1 kb) high-density crossbar arrays using a Si-based memristive system. A two-terminal hysteretic resistive switch (memristive device) is formed at each crosspoint of the array and can be addressed with high yield and ON/OFF ratio. The crossbar array can be implemented as either a resistive random-access-memory (RRAM) or a write-once type memory depending on the devic...

The tremendous growth of the Internet coupled with newly emerging applications has created a vital need for multicast traffic support by backbone routers and ATM switches. In this paper, we first introduce the multicast traffic scheduling problem. We focus our study on the multicast traffic scheduling in crossbar based input queued (IQ) switches. Due to the centralized scheduling complexity in ...

The buffered crossbar switch architecture has recently gained considerable research attention. In such a switch, besides normal input and output queues, a small buffer is associated with each crosspoint. Due to the introduction of crossbar buffers, output and input contention is eliminated, and the scheduling process is greatly simplified. We analyze the performance of switch policies by means ...

A scheduling algorithm is proposed for lightweight on-chip crossbar switch in on-chip networks. The proposed NA-MOO algorithm distributes the arbitration computing over all of the crossbar fabric nodes. Its implementation shows that it can reduce > 60% area and > 20% computation delay compared to conventional round robin based SLIP algorithm. Its feasibility is analyzed by using a SoC for HDTV ...

As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects— whether on-chip or off-chip—is rapidly increasing. Traditional interconnects like buses, point-to-point wires and regular topologies may suffer from poor resource sharing in the time and space domains, leading to high contention or low resource utilization. In this paper, we propose a d...

A high speed switch is a critical component of multiprocessors. Multistage Interconnection Network (MIN) has been utilized as a switch for connection processors and memory modules in multiprocessors. Unlike the crossbar, it consists of small switching elements, and provides a high bandwidth with relatively small hardware. Most of traditional MINs are blocking networks and packets are transferre...

The task which includes computing of non-conflict schedule for crossbar switch node of packet commutation is NP-hard. After checking their efficiency with throughput modelling by uniform load traffic, the check for non-uniform traffic is required. In the presented paper we propose a procedure of calculating the upper boundary of throughput for crossbar packet switch node. The results of the com...

This paper proposes an efficient topology synthesis method for on-chip interconnection network based on crossbar switches. The efficiency of topology synthesis methods is often measured by two metrics—the quality of the synthesized topology and synthesis time. These two metrics are critically determined by the definition of the topology design space and the exploration method. Furthermore, an e...

Current technology trends make it feasible to build extrememly high band-width connection networks. Development of high performance and cost-eeective switches is of paramount importance in such networks, and is an area of heavy current research. Two most important components of modern switches are queueing and scheduling. This paper presents a brief survey of unicast and multicast scheduling al...