latched before the output signals in the bundle are stable. The algorithm used to detect delay faults in the processing logic of the ASC is similar to that exploited in delay testing of combinational circuits [15]. Basically, the pair of test patterns < , > must be applied to the inputs of the combinational circuit to detect its delay path fault. The pair < , > is made up of < @ , @ >, where an...

Sequential networks contain combinational logic blocks separated by registers. Application of combinational logic minimization techniques to the separate logic blocks results in improvement that is restricted by the placement of the registers; information about logical dependencies between blocks separated by registers is not utilized. Temporarily moving all the registers to the periphery of a ...

IR-drop problem is becoming more and more important. Previous works dealing with power/ground (P/G) network peak current reduction to reduce the IR-drop problem only focus on synchronous sequential logic circuits which consider the combinational parts as unchangeable [4],[5]. However, some large combinational circuits which work alone in one clock cycle can create large current peaks and induce...

We address three related issues on timing characterization of combinational modules. We first introduce a new notion called timing safe-replaceability as a way of comparing the timing characteristics of two combinational modules formally. This notion allows us to determine whether a new module is a safe replacement of an original module in terms of timing under any surrounding environment. Seco...

It is very important for bank to control the credit risk of guarantee loan or combinational loan by evaluating the joint default risk of different enterprises. Firstly we apply a combinational copula function to measure the joint default risk of two enterprises with credit rating information; secondly the default intensity model is intended to analyze the default time distribution; thirdly we u...

Boolean Expression Diagrams (BEDs) is a new data structure for representing and manipulating Boolean functions. BEDs are a generalization of Binary Decision Diagrams (BDDs) that are capable of representing any Boolean circuit in linear space and still maintain many of the desirable properties of BDDs. This paper demonstrates that BEDs are well suited for solving the combinational logic-level ve...

The accepted wisdom is that combinational circuits must have acyclic (i.e., loop-free or feed-forward) topologies. And yet simple examples suggest that this need not be so. Prior work advocated the design of cyclic combinational circuits (i.e., circuits with loops or feedback paths). A methodology was proposed for optimizing circuits by introducing cycles at the technologyindependent stage of s...

Effect of Combinational Changes Catheter Size and its Negative Suction Pressure on Hemodynamic Parameters Mechanical Ventilation Patients