The very fast growing market of portable equipment is increasing interest in low power integrates circuit. So, designing low power integrated circuits requires reduction of supply voltages and interconnection parasitic to minimum but reduction in supply voltage implies series of problems in circuit design. To overcome these issues, an Ultra low power low voltage two stage class AB CMOS fully di...

This low-power RD modulator targets the DVBH requirements and achieves about 10 bit with 6-MHz signal band. Suitable topological modifications enable the realization of a third order modulator with two op-amps. Moreover, a technique for swing reduction of the last op-amp strongly reduces the number of comparators in the quantizer. The power reduction techniques limit the consumption to 6.18 mW,...

In low voltage low power CMOS systems both the high input offset and noise voltages of MOSFETs and also the moderate gain of op amps limit the accuracy of analog circuits. In this paper we present a new high-accuracy instrumentation amplifier; this circuit topology is the first ever reported "non-autozero" instrumentation amplifier which allows to compensate, beside the input offset and noise v...

As CMOS processes continue to scale to smaller dimensions, the increased fT of the devices and smaller parasitic capacitance allow for more power efficient and faster digital circuits to be made. But at the same time, output impedance of transistors has gone down, as have the power supply voltages, and leakage currents have increased. These changes in the technology have made analog design more...

approved: Gabor C. Temes In this thesis, novel design techniques have been proposed for implementing highlinearity SC circuits in a standard digital CMOS process. They use nonlinear MOSFET capacitors instead of linear double-poly capacitors. To reduce their nonlinearities, a bias voltage is applied to keep MOSFET capacitors in their accumulation regions. For further reduction of distortion, two...

A simple scheme for rail to rail op-amp operation is introduced. The input stage uses complementary differential pairs but only one pair is active at a time. It uses very compact control circuitry. Experimental verification is provided from a test chip prototype in 0.5 μm CMOS technology.

A low-noise CMOS amplifier operating at a low supply voltage is developed using the two noise reduction techniques of autozeroing and chopper stabilization. The proposed amplifier utilizes a feedback with virtual grounded input-switches and a multiple-output switched opamp. The low-noise amplifier fabricated in a 0.18-μm CMOS technology achieved 50-nV/ √ Hz input noise at 1-MHz chopping and 0.5...

This paper addresses the difficulty of designing 1-V capable analog circuits in standard digital complementary metal–oxide–semiconductor (CMOS) technology. Design techniques for facilitating 1-V operation are discussed and 1-V analog building block circuits are presented. Most of these circuits use the bulk-driving technique to circumvent the metal– oxide–semiconductor field-effect transistor t...

An 8-bit 40-MS/s low power Multiplying Digital-toAnalog Converter (MDAC) for a pipelined-to-Analog to Digital converter (ADC) is presented. The conventional dedicated operational amplifier (Op-Amp) is performed by using telescopic architecture that features low power and less-area. Further reduction of power and area is achieved by using multifunction 1.5bit/stage MDAC architecture. The design ...