Clock and data recovery (CDR) circuits incorporating bangbang (binary) phase detectors (PDs) have recently found wide usage. In contrast to their linear counterparts, bang-bang PDs relax the speed and precision required of flipflops and other circuits in the signal path, reducing the complexity and the power dissipation. However, the heavily nonlinear nature of these PDs makes the loop analysis...

Modern communication and computer systems require rapid (Gbps), efficient and large bandwidth data transfers. Agressive scaling of digital integrated systems allow buses and communication controller circuits to be integrated with the microprocessor on the same chip. The Peripheral Component Interconnect Express (PCIe) protocol handles all communcation between the central processing unit (CPU) a...

A multilevel clock and data recovery (CDR) circuit for highspeed serial data transmission was designed using the IBM 6HP 0.25 μm SiGe BiCMOS process technology. The circuit extracts the clock from a 32 Gb/s 4-level pulse amplitude modulated (PAM-4) input signal and outputs four channels of retimed NRZ data at 8 Gb/s per channel. The CDR design incorporates a PAM-4 to 2-bit-binary converter, a p...

A 200-Mbps 2-Gbps continuous-rate clock-anddata-recovery (CDR) circuit using half-rate clocking is presented. To detect the data with wide-range bit rates, a frequency tracing circuit (FTC) is used to aid the frequency acquisition. A wide-range and low gain voltage-controlled oscillator (VCO) is also presented by using analog and digital controlled mechanisms. A two-level bang-bang phase detect...

A 4-Gb/s clock and data recovery (CDR) circuit is realized in a 0.25m standard CMOS technology. The CDR circuit exploits 1 8-rate clock technique to facilitate the design of a voltage-controlled oscillator (VCO) and to eliminate the need of 1:4 demultiplexer, thereby achieving low power consumption. The VCO incorporates the ring oscillator configuration with active inductor loads, generating fo...

The applications envisioned for sensor networks require collaborative execution of a distributed task amongst a large set of sensor nodes. This is realized by exchanging messages that are time-stamped using the local clocks on the nodes. Therefore, time synchronization becomes an indispensable piece of infrastructure in such systems. We propose a design of synchronous clock using digital tune m...

Optical packet switching (OPS) networks are promising to accommodate the growing traffic and reduce power consumption in data center communications. OPS with nanosecond time require clock recovery (CDR) circuits. The CDR can be achieved by utilizing a global frequency-synchronized reference for both transmitters (TX) receivers (RX) adopting phase compensation scheme, which leads predictably man...

Abstract The DUNE neutrino experiment far detector has a fiducial mass of 40 kt. O(1M) readout channels are distributed over the four 10 kt modules and need to be synchronized with respect each other precision O(10 ns). entire system needs GPS time O(100 reliable, simple affordable. Clock synchronization information encoded on same fibre using protocol based duty cycle shift keying (DCSK) 8b10b...

This paper presents the first fully integrated radiation-tolerant All-Digital Phase-Locked Loop (PLL) and Clock Data Recovery (CDR) circuit for wireline communication applications. Several radiation hardening techniques are proposed to achieve state-of-the-art immunity Single-Event Effects (SEEs) up 62.5 MeV cm2 mg?1 as well tolerance Total Ionizing Dose (TID) exceeding 1.5 Grad. The LC Digital...

With the great increases in data transmission rate requirements, analog-to-digital converter (ADC)-based wireline receivers have received more and attention due to their flexible powerful equalization capabilities. Considering power consumption, baud-rate Mueller–Muller clock recovery (MM-CDR) circuits are widely used ADC-based since MM-CDR only need one sample signal per unit interval (UI). Ho...