The StrongARM SA-1100 is a high-speed low-power processor aimed at embedded and portable applications. Its architecture features virtual caches and TLBs which are not tagged by an address-space identifier. Consequently, context switches on that processor are potentially very expensive, as they may require complete flushes of TLBs and

In this work, we optimise the Android IO stack for user-level filesystem. Android imposes user-level filesystem over native filesystem partition to provide flexibility in managing the internal storage space and to maintain host compatibility. The overhead of user-level filesystem is prohibitively large and the native storage bandwidth is significantly under-utilised. We overhauled the FUSE laye...

Concolic testing has been proposed as an effective technique to automatically test software. The goal of concolic testing is to generate test inputs to find faults by executing as many paths of a program as possible. However, due to the large state space, it is unrealistic to consider all of the program paths for test input generation. Rather than exploring the paths based on the structure of t...

Sharing buffer space between switch ports greatly improves the pelformunee of the switching systems. Howevel; sharing buffers in a fair Manner is not an easy task. In this paper we propose a high-performunee ATM switching system with fairly and completely shared buffers. The core of the proposed switching system is a novel buffer management mechanism with which buffer space in the switching sys...

This paper proposes DAMQSV and DAMQS algorithms for systems on chip applications that require an interconnection network. The proposed schemes are based on a DAMQ buffer hardware design. DAMQSV and DAMQS are excellent schemes to optimize buffer management providing a good throughput when the network has a larger load. They can utilize significantly less buffer space without sacrificing the netw...

Many embedded devices used to control critical infrastructure assets are based on the Harvard architecture. This architecture separates data and program memory into independent address spaces, unlike the von Neumann architecture, which uses a single address space for data and program code. Buffer overflow attacks in desktop and server platforms based on the von Neumann model have been studied e...

the voltammetric behaviour of sulfadoxine (sdn) was studied at a glassy carbon electrode in 0.2 m phosphate buffer solutions using cyclic, differential-pulse (dpv) and square wave voltammetry (swv). the dependence of the current on ph, concentration, and scan rate was investigated to optimize the experimental conditions for the determination of sdn. the oxidation process was shown to be diffusi...

Low-level attacks often rely on guessing absolute or relative memory addresses. Layout randomization aims to thwart such attacks. In this paper, we study layout randomization in a setting in which arrays and functions can be stored in memory. Our results relate layout randomization to language-level protection mechanisms, namely to the use of abstract locations (rather than integer addresses). ...

We introduce Fracture, a novel framework that transforms and modernizes the basic process abstraction. By “fracturing” an application into logical modules, Fracture enables powerful and novel run-time configurations that improve run-time testing, application availability, and general robustness, all in a generic and incremental manner. We demonstrate the utility of fracturing via in-depth case ...

The general-purpose precise interrupt mechanism, which has long been used to handle exceptional conditions that occur infrequently, is now being used increasingly often to handle conditions that are neither exceptional nor infrequent. One example is the use of interrupts to perform memory management-e.g., to handle translation lookaside buffer (TLB) misses in today’s microprocessors. Because th...