How to resolve the control flow breaking caused by the branch instructions is a major issue in modern deep pipeline processor design. Our project is based on the paper of J. Stark et. al. [1], a variable length path branch predictor. It uses the branch path information for prediction, and change the length of the path dynamically based on the profiling of the application. It shows that a “cleve...

Recently, there have been significant advances in deep neural networks (DNNs) and they have shown superior performance in audio and image processing. In this paper, we explore DNNs to push the limit for branch prediction. We treat branch prediction as a classification problem and explore both deep convolutional neural networks (CNNs) and deep belief networks (DBNs) for branch prediction. We ana...

The paper introduces a dynamic branch prediction scheme suitable for energy-aware Very Long Instruction Word (VLIW) processors. The proposed technique is based on a compiler hint mechanism to filter the accesses to the branch predictor blocks. We define a configurable hint instruction which anticipates some static information about the upcoming branch to reduce the hardware involved in the pred...

As the issue rate and depth of pipelining of high performance Superscalar processors increase, the importance of an excellent b r a n c h predictor becomes more vital to delivering the potential performance of a wide-issue, deep pipelined microarchitecture. We propose a new dynamic branch predictor (Two-Level Adaptive Branch Prediction) that achieves substantially higher accuracy than any other...

During the 1990s Two-level Adaptive Branch Predictors were developed to meet the requirement for accurate branch prediction in high-performance superscalar processors. However, while two-level adaptive predictors achieve very high prediction rates, they tend to be very costly. In particular, the size of the second level Pattern History Table (PHT) increases exponentially as a function of histor...

We describe a method for supporting static branch prediction on a decoupled fetch-execute pipeline. Using instruction buffers to decouple instruction fetch from the execute pipeline is an effective way to minimize instruction cache penalties by allowing instruction fetch and stall miss handling to proceed independent of the execution pipeline. Dynamic branch prediction is typically used with su...

The main aim of this research is to propose a new Two-Level Adaptive Branch Prediction scheme, based on additional correlation information. Conventional two-level adaptive branch prediction exploits the correlation between the outcome of a branch and the path followed through a program to reach the branch. Typically the program path is identified by recording whether each branch on the path is ...

The prediction by partial matching (PPM) algorithm has been well known for its high prediction accuracy. Recent proposals of PPM-like predictors confirm its effectiveness on branch prediction. In this paper, we introduce a new branch prediction algorithm, named Prediction by combining Multiple Partial Matches (PMPM). The PMPM algorithm selectively combines multiple matches instead of using the ...

The techniques of Instruction Level Parallelism (ILP) and pipeline have been used well to speed up the execution of instructions. The conditional branches are the critical factor to the effectiveness of a deep pipeline since the branch instructions can always break the flow of instructions through the pipeline and result in high execution cost. In order to achieve better CPU performance, many s...

Branch instructions create barriers to instruction prefetching, greatly reducing the fine-grained parallelism of programs. Branch prediction is a common method for solving this problem. We first present four lemmata in this paper describing the relationships among branch prediction hit rate and system performance, hardware efficiency, and branch prediction overhead. We then propose a branch pre...