Reseeding is used to improve fault coverage in pseudo-random testing. Most of the work done on reseeding is based on storing the seeds in an external tester. Besides its high cost, testing using automatic test equipment (ATE) makes it hard to test the circuit while in the system. In this paper, we present a technique for built-in reseeding. Our technique requires no storage for the seeds. The s...

Increasing number of pins or gates in the latest LSI’s requires a lot of testing resources. The conventional scan-based testing requires a costly tester (ATE) equipped with a lot of pin electronics. Since reducing the testing cost is a crucial issue in industry, we have introduced an approach using scan-based logic BIST to solve this problem. The logic BIST has applied to many ASIC design chips...

We present the application of a deterministic logic BIST scheme on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100K gates with 10,000 test patterns, at a total area cost for BIST hardware of typically 5%-15%. It is demonstrated that a tradeoff is possible between test quality, test time, and silicon a...

Diagnosing failing vectors in a Built-In Self Test (BIST) environment is a difficult task because of the highly compressed signature coming out of the Multiple Input Shift Register (MISR). The root cause of the failure must be initially narrowed down to the failing vectors and also the scan cells at which mismatches occurred. In this work, we propose a method for accurately determining the firs...

The generation of significant power droop (PD) during at-speed test performed by Logic BIST is a serious concern for modern ICs. In fact, the PD originated during test may delay signal transitions of the circuit under test (CUT): an effect that may be erroneously recognized as delay faults, with consequent erroneous generation of test fails, and increase in yield loss. In this paper, we propose...

We present a new low-power BIST (built-in-self-test) for sequential circuits. State correlation analysis is first performed on the flip-flop values in the relaxed, compacted sequence for the undetected faults to extract spatial correlations among the flip-flops. The extracted spatial correlation matrix not only provides additional metrics through which the scan order may be altered, but also al...

One of the tenets of equilibrium asset pricing models is that expected return of an asset is positively related to its risk (price variability of the asset). In other words, it is expected that assets with higher expected returns are also the ones with higher risk, or assets with lower risk are the ones with lower expected returns. The logic behind this idea is actually is simple and intuitive:...

The main aim of this paper is to design and implement efficient UART and test the UART with built in self testing technique . A new Test pattern generator is simulated and used in BIST architecture in order to reduce power dissipation. As we know that power dissipation is more during the test mode than in normal mode hence In this project the pattern generator used is the low power pattern gene...

The increasing growth of sub-micron technology has resulted in the difficulty of testing. Design and test engineers have left no choice but to accept new responsibilities that had been performed by group of technicians in the previous years. Design engineers who do not design systems with full testability had increased the possibility of product failures and missed market opportunities. BIST is...