Experiments were designed to investigate the suitability of a combination of a short manual teat stimulation with a short latency period before teat cup attachment to induce and maintain oxytocin release and milk ejection without interruption. In Experiment 1, seven dairy cows in mid lactation were manually pre-stimulated for 15, 30 or 45 s, followed by either 30 s or 45 s of latency period. It...

This technical report describes the construction of an inexpensive Ethernet Bridge built from an obsolete Pentium PC (IBM PC 300GL Pentium 166MMX ) and Ethernet cards. The report outlines a simple procedure for estimating the latency of the bridge. Results are presented for the timestamping accuracy of the bridge, the average latency and FreeBSD ping characteristics. The bridge can be used as a...

This paper presents a technology mapper that optimizes the average performance of asynchronous burst-mode control circuits. More specifically, the mapper can be directed to minimize either the average latency or the average cycle time of the circuit. The input to the mapper is a burst-mode specification and its NAND-decomposed unmapped network. The mapper pre-processes the circuit’s specificati...

vestibular involvements have long been observed in otosclerotic patients. among vestibular structures saccule has the closest anatomical proximity to the sclerotic foci, so it is the most prone vestibular structure to be affected during the otosclerosis process. the aim of this study was to investigate the saccular function in patients suffering from otosclerosis, by means of vestibular evoked ...

By perianal electrical stimulation and EMG recording from the external anal sphincter the anal reflex was constantly present in normal subjects. The latency decreased within certain limits with increasing stimulation to an average minimum latency of 50 ms (SD 10.5). There was no difference between the minimum latency in normal subjects and patients with suprasegmental lesions of the CNS. The la...

In this paper we introduce concepts of a potential fault latency and a real fault latency for Finite State Machines (FSMs). The potential latency defines a minimal value of the possible latency for an FSM, while the real latency relates to the certain implementation of the FSM. A method for investigation of latencies for online checking FSMs is described. This technique is based on selection of...