This paper presents the current status of the forth generation BSIM model and issues of modeling CMOS based devices with nanometer dimensions. Due to the divergence of device structures in sub-0.1 m gate length, it is more and more difficult to describe the device physics accurately and efficiently. In order to have a practical model with enough flexibility to accommodate a wide variety of tech...

The paper proposed a new design for implementing a Single Edge Triggered Flip-Flop. In this work, comparative analysis of six existing flip-flop designs along with the proposed design is made. In the proposed design the number of clocked transistors is reduced to decrease the power consumption and it also employs the conditional feedback to reduce the short-circuit currents. All simulations are...

The spatial wave-function switched field effect transistor (SWSFET) has two or three low band-gap quantum well channels inside the substrate of the semiconductor. Applied voltage at the gate region of the SWSFET, switches the charge carrier concentration in different channels from source to drain region. The switching of electron wave function in different channels can be explained by the devic...

Bulk-driven MOSFET technique meets the low-voltage and low-power requirements demanded in the modern analog circuit design. Due to submicron/nanometer technologies and critical short-channel effects, choosing a suitable MOSFET model for circuit design becomes increasingly important. However, the conventional MOSFET models normally set up for the typical gate-driven applications may not perform ...

SOI means Silicon on Insulator. This type of transistors has Silicon-Insulator-Silicon substrate which is different from conventional MOSFET structure where metal layer is used on the top of Insulator [1, . Now a days, the width of the oxide of a MOSFET is reduced from 300nm to 1.2nm and even less with scaling in technology. If it is further reduced, the leakage problems (majorly Sub-threshold ...

Magnitude comparison is one of the basic functions used for sorting in microprocessor, digital signal processing, so a high performance, effective magnitude comparator is required. The main objective of this paper is to provide new low power, area solution for Very Large Scale Integration (VLSI) designers. At circuit level, Hybrid PTL/CMOS Logic style gives best results over CMOS only and PTL o...

In this study, we analyzed the total ionizing dose (TID) effect characteristics of p-type FinFET and Nanowire FET (NW-FET) according to structural aspect through comparison two devices. Similar n-type devices, NW-FETs are less affected than FinFETs by TID effect. For inverter circuit simulation, both n- p-types NW-FET were regarding The operation considering was verified using Berkeley short-ch...

In this paper the design of a new high-speed current mode BiCMOS logic circuits isproposed. By altering the threshold detector circuit of the conventional current mode logic circuitsand applying the multiple value logic (MVL) approach the number of transistors in basic logicoperators are significantly reduced and hence a reduction of chip area and power dissipation as wellas an increase in spee...

Ion-optical calculations are often performed as a first step when designing magnetic systems. As a second step Monte-Carlo simulations are performed of EVaporation Residue (EVR) trajectories through the separator, varying parameters like target thickness, gas pressure and magnet field. Such a program is very useful to optimize all system parameters and to plan and to prepare experiments. The ne...