نتایج جستجو برای: حافظه sram

تعداد نتایج: 6868  

S. Kassa, S. Nema

This paper introduces a peculiar approach of designing Static Random Access Memory (SRAM) memory cell in Quantum-dot Cellular Automata (QCA) technique. The proposed design consists of one 3-input MG, one 5-input MG in addition to a (2×1) Multiplexer block utilizing the loop-based approach. The simulation results reveals the excellence of the proposed design. The proposed SRAM cell achieves 16% ...

2016
Sonam Jain

Low power SRAM memory designs has become challenging for portable device applications. Semiconductor/ VLSI industry growth has exponentially demanding low leakage power SRAM designs for high performance chips and microprocessors. To get optimized standard cell memory design for battery operated devices at deep sub micron CMOS technology, a low leakage Asynchronous 8T SRAM is proposed. In this p...

2014
Peng Wang Chengxiang Jiang Zhen Li Qiannan Xue Yi Tian

The application of Static Random-Access Memory (SRAM), becomes more and more widely in aviation. However, the large amount of SRAM cells is very vulnerable to radiation included single-event upset (SEU). Based on the detection requirement of SRAM’s SEU, the detected circuit of the SEU on SRAM is designed. Then the method of redundancy check is used in the reinforcement of the SEU. The test resu...

2015
J. Madhuri

In low power SRAM memory cell design Power dissipation through standby leakage and dynamic loss is a major problem. this paper is mainly based on low power cell operation and delay of SRAM designing this paper presents a novel technique to reduce short circuit power. The differential SRAM for ultra low voltage design for Schmitt trigger (ST) is analyzed using 180nm CMOS technology. Schmitt trig...

Journal: :IEEE Trans. VLSI Syst. 2016
Moein Kianpour Reza Sabbaghi-Nadooshan

Application of quantum-dot cellular automata (QCA) technology as an alternative to CMOS technology on the nanoscale has a promising future; QCA is an interesting technology for building memory. The proposed design and simulation of a new memory cell structure based on QCA with a minimum delay, area, and complexity is presented to implement a static random access memory (SRAM). This paper presen...

2009
Seng Oon Toh Yasumasa Tsukamoto Zheng Guo Lauren Jones Tsu-Jae King Liu Borivoje Nikolić

An alternating-bias random telegraph signal (RTS) characterization technique is presented, which shortens measurement time by 10x and also produces more accurate statistical distributions of RTS amplitudes. Measurements of RTS amplitudes in 45nm SRAM transistor Ids and cell write margin are reported and used to demonstrate a complex dependence of write margin on RTS in multiple transistors. Fai...

Journal: :Microelectronics Journal 2014
Hooman Farkhani Ali Peiravi Farshad Moradi

A new asymmetric 6T-SRAM cell design is presented for low-voltage low-power operation under process variations. The write margin of the proposed cell is improved by the use of a new write-assist technique. Simulation results in 65 nm technology show that the proposed cell achieves the same RSNM as the asymmetric 5T-SRAM cell and 77% higher RSNM than the standard 6T-SRAM cell while it is able to...

2011
Shreyas Kumar Krishnappa Hamid Mahmoodi

Bias Temperature Instability (BTI) causes significant threshold voltage shift in MOSFET using Hafnium-dioxide (HfO2) High-k dielectric material. Negative BTI and Positive BTI are two types of BTI effects observed in p-channel and n-channel MOSFET. BTI affects the stability and reliability of conventional six transistor (6T) SRAM design in nano-scale CMOS technology. Eight transistor (8T) and Te...

Journal: :IEICE Transactions 2013
Shusuke Yoshimoto Shunsuke Okumura Koji Nii Hiroshi Kawaguchi Masahiko Yoshimoto

This paper presents a proposed NMOS-centered 6T SRAM cell layout that reduces a neutron-induced multiple-cell-upset (MCU) SER on a same wordline. We implemented an 1-Mb SRAM macro in a 65-nm CMOS process and irradiated neutrons as a neutron-accelerated test to evaluate the MCU SER. The proposed 6T SRAM macro improves the horizontal MCU SER by 67–98% compared with a general macro that has PMOS-c...

Journal: :Information Security Journal: A Global Perspective 2013
Mikhail Platonov Josef Hlavác Róbert Lórencz

Secret keys are usually stored in an nonvolatile memory, which can be hard to secure. An alternative is to generate the keys “on-the-fly” by using the inherent uniqueness of a device based on the manufacturing process variations. This is realized by physical unclonable functions (PUFs). A promising approach is to construct an intrinsic PUF based on SRAM memory, since many electronic devices hav...

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