The Computer Systems Laboratory has been involved in a VLSI research program for one and a half years. The major areas under investigation have included: analysis and synthesis design aids, applications of VLSI to computer graphics, !he design of a personal workstation, special purpose chip design, VLSI computer architectures, and hardware specification and verification. Progress on these resea...

The Steiner minimum tree problem, which asks for a minimum-length interconnection of a given set of terminals in the plane, is one of the fundamental problems in Very Large Scale Integration (VLSI) physical design. Although advances in VLSI manufacturing technologies have introduced additional routing objectives, minimum length continues to be the primary objective when routing non-critical net...

A VLSI circuit complexity analysis for low-power decoder designs is presented. Two low-complexity adaptive decoder architectures incorporating the ~ecursive systematic codes (turbo-codes) and the block-codes are considered in this paper. The system performance degradation due to the algorithm approximations for realizing the low complexity decoders is also investigated. The decoders are impleme...

For the high speed processing of databases, it is fundamental to introduce various VLSI architectures to the processing of basic functions. Especially, sort and batch search requires high speed modules. The VLSI algorithms of them must make use of the time necessary for the transfer of a large amount of data to and from the modules. These modules should be nonprogrammable in order to avoid seri...

With the current advances in VLSI technology, traditional algorithms for Residue Number System (RNS) based architectures should be reevaluated to explore the new technology dimensions. In this brief, we introduce A @(log n ) algorithm for large moduli multiplication for RNS based architectures. A systolic array has been designed to perform the modulo multiplication Algorithm. The proposed modul...

The rapid advances in the very large scale integrated (VLSI) technology has created a flurry of research in designing future computer architectures. Many methods have been developed for parallel processing of algorithms by directly mapping them onto parallel architectures. A procedure, based on the mathematical transformation of the index set and dependence vectors of an algorithm, is developed...

Real-time vision-based vehicle navigation tasks are typically computationally intensive and significantly complex in terms of resources used. Moreover, mobile applications of navigation systems place severe constraints on their size and power consumption. These constraints can be satisfied by using parallel image processing architectures and parallel control algorithms implemented with analog V...

Area and Energy Efficient VLSI Architectures for Low -Density Parity-Check Decoders Using an On-the-Fly Computation. (December 2006) Kiran Kumar Gunnam, M.S., Texas A&M University Co-Chairs of Advisory Committee: Dr. Gwan Choi Dr. Scott Miller The VLSI implementation complexity of a low density parity check (LDPC) decoder is largely influenced by the interconnect and the storage requirements. T...