An efficient architecture for low jitter All Digital Phase Locked Loop (ADPLL) suitable for high speed SoC applications is presented in this paper. The ADPLL is designed using standard cells and described by Hardware Description Language (HDL). The ADPLL implemented in a 90 nm CMOS process can operate from 10 to 200 MHz and achieve worst case frequency acquisition in 14 reference clock cycles. ...

This paper aims to compare different design alternatives of hardware-in-the-loop (HIL) for emulating power converters in Field Programmable Gate Arrays (FPGAs). It proposes various numerical formats (fixed and floating-point) approaches (pure VHSIC Hardware Description Language (VHDL), Intellectual Properties (IPs), automated MATLAB HDL code, High-Level Synthesis (HLS)) converters. Although the...

Reconfigurable systolic arrays can be adapted to efficiently resolve a wide spectrum of computational problems; parallelism is naturally explored in systolic arrays and reconfigurability allows for redefinition of the interconnections and operations even during run time (dynamically). We present a reconfigurable systolic architecture that can be applied for the efficient treatment of several dy...

In this document, we focus on how to design cyclic redundancy check (CRC) circuits with different 5G polynomial divisor using very high-speed integrated circuit (VHSIC) hardware description language (VHDL) integrate in field-programmable gate array (FPGA) suitable kit a code. The between designed came from the of data size according polynomials requirements conditions since there are huge syste...

In this paper we present the implementation of Error Back Propagation Training Algorithm (EBPT) in VHSIC Hardware Descriptive Language (VHDL) platform for two standard benchmark problems of Nonlinear Classification of XOR function and Sine wave Generation. The effect of variation of learning parameters on accuracy of the output and speed of convergence of the algorithm are presented. Improved s...

This paper presents the simulation results of binary digital modulation schemes. In this paper, for BASK and BPSK modulation techniques used FPGA algorithm, multiplier don't using. If multiplier block is used for multiplication bit stream with carrier signal, used time will rises. In addition using multiplier block obtained simulation results were analyzed and compared to other simulation ...

This paper présents extended Works on BPSK Modulation at Low Bit Rate and also presents Simulation results and FPGA implementation of BPSK demodulation at Low Bit Rate 1200 bits/second on Altera Stratix III Development Board. Here Binary Sequence ,Carrier Frequency and sampling frequency are user controllable in BPSK modulation that was designed already. So this paper present Design of BPSK Dem...

Specialized accelerators deliver orders of a magnitude higher performance than general-purpose processors. The ever-changing nature modern workloads is pushing the adoption Field Programmable Gate Arrays (FPGAs) as substrate choice. However, FPGAs are hard to program directly using Hardware Description Languages (HDLs). Even high-level HDLs, e.g., Spatial and Chisel, still require hardware expe...

by Mark Dean Mueller With the increasing use of mixed signal analog and digital technologies in circuit design, there becomes a growing need for a method to simulate such circuits quickly, easily and accurately. Modeling the components structurally with an analog simulation tool is a common technique. A more powerful method would be to behaviorally model both types of components at a higher lev...

Design of a Fuzzy Logic Controller (FLC) requires more design decisions than usual, for example rule base, inference engine, defuzzification, and data preand post processing. This project is a humble effort to implement an FLC using VHDL for motor control. There are three parts to fuzzy controller, the fuzzification of the inputs, the defuzzification of the outputs, and the rule base. The contr...