In this paper, we have designed a new variable latency adder and its implementation of decimation filter. There are multiple ways to implement a decimationfilter. This filter design combination of CIC (cascaded-integrator-comb) filter and HB (half band) filter as the decimator filter to reduce the frequency sample rate conversion and detail of the implementation step to realize this design in h...

Abstract -This paper presents an architecture for a high-speed carry select adder with very long bit lengths utilizing a conflict-free bypass scheme. The proposed scheme has almost half the number of transistors and is faster than a conventional carry select adder. A comparative study is also made between the proposed adder and a Manchester carry chain adder which shows that the proposed scheme...

We propose and demonstrate both a binary and ternary adder circuit based on a resonant tunneling diode (RTD) and a bipolar transistor. The basic switching cell consists of an RTD in series with the base of a bipolar transistor. The RTD is used to set a threshold voltage for the switching of the transistor.

The realisation of Delay-Insensitive (DI) asynchronous circuits with a CMOS ternary logic is described in this paper. The main advantage of temary logic is the easy realisation of a handshake protocol that significantly reduces the communication requirement, one of the major drawback of asynchronous logic. It is shown how general purpose delay-insensitive circuits are designed with standard ter...

The Pockels effect in periodically poled lithium niobate made it possible to switch optical signals between two orthogonal optical linear polarizations of the vertical and horizontal polarization states. Based on this effect, we demonstrated polarization-based binary optical logic gates: AND, and OR gates. By combining these basic gates with other polarization-based optical logic gates such as ...