With the improvement of System-on-Chip integration, chip requires an increasingly large amount test data. To solve contradiction between storage capacity and bandwidth automatic equipment (ATE), a new method data compression/decompression is proposed based on annular scan chain. Corresponding fault bits different patterns are incompatible, moving in chain, makes all corresponding be compatible ...

Due to advance in semiconductor manufacturing technology, integration of whole electronics system on a single chip is feasible. Starting with baseline CMOS logic, semiconductor wafer manufacturers have gradually added to their portfolio embedded memory (SRAM, OPT, Flash), mixed signal devices, RF devices, and even MEMS. Because it offers many advantages over traditional multiple-chip solutions,...

The variety of interconnection structures presently nowadays for SoC (System-on-Chip), bus and networkson-Chip NoCs, each of them with a wide set of setup parameters, provides a huge amount of design alternatives. Although the interconnection structure is a key SoC component, there are few design tools in order to set the appropriate configuration parameters for a given application at the first...

Electromagnetic interference (EMI), once the exclusive concern of equipment designers working with high-speed signals, is no longer limited to a narrow class of high-end applications. Continued innovation in semiconductor technology has resulted in the ready availability of cost-effective, high-performance system-on-chip (SoC) devices, microcontrollers (MCUs), processors, digital signal process...

The electronics industry has entered the era of multimillion-gate chips, and there is no turning back. This technology promises new levels of integration on a single chip, called the system-on-a-chip (SoC) design, but also presents significant challenges to the chip designers. Processing cores on a single chipmay number well into the high tens within the next decade, given the current rate of a...

This paper describes the methodology employed by the IBM Microelectronics Division for the design of its Blue Logic applicationspecific integrated circuits (ASICs) and system-on-a-chip (SoC) designs. This methodology is used by both IBM ASIC and SoC designers, as well as OEM customers. A key focus of the IBM ASIC/SoC methodology, outlined in the first section of this paper, is the first-time-ri...

System-on-a-Chip is an evolving definition where a current generation system implemented with multiple chips on a board translates to a system-on-a-chip for the next generation. This is enabled by advances in the semiconductor technology which support increasing levels of single chip integration. For system components which can be efficiently implemented in CMOS, integrating them on a single ch...

In this paper, a modified programmable twisted ring counter (MPTRC) based on-chip test generation scheme is proposed. It is used as built-in-self-test (BIST) pattern generator for high performance circuits with simple test control. This method is used to achieve low power and reduced test time for digital circuits. The MPTRC module is designed with Cadence NClaunch platform using Verilog HDL an...

With the increase in chip size and complexity, the direct or bus interconnects in conventional SoC test control models are rather restricted. In this paper, we propose a new distributed multihop wireless test control network based on the recent development in “radio-on-chip” technology. The proposed architecture consists of three basic components, the test scheduler, the resource configurators,...

Tokyo, January 19, 2009 — Renesas Technology Corp. today announced the SH7776 (SH-Navi3), a dual-core system-on-chip (SoC) device with on-chip enhanced graphics functions and a highperformance image recognition processing function for the next generation high-performance car information terminals that evolved from car navigation systems. The SH7776 (SH-Navi3) integrates two CPU cores on a singl...