In the paper we consider a promising universal reconfigurable supercomputer, computing nodes of which are device Arcturus. It was developed at Supercomputers and Neurocomputers Research Center (Taganrog) based on modern Xilinx FPGAs UltraScale+ family HBM-series. The purpose is to achieve highest computational layout density, ensure balanced power supply cooling, as well implementation powerful...

We are in an era where computational building blocks are plentiful and inexpensive. A single chip today can hold over 100 1GHz °oating-point units for a total performance of 100 GFLOPS/chip. Many graphics chips achieve 80GFLOPS and over 1TOP rendering performance, and cost less than $100. Embedded processors are less powerful, but incredibly cheap. It is fair to say that a raw GFLOPS costs less...

IEEE P1596, the Scalable Coherent Interface (formerly known as SuperBus) is based on experience gained while developing Fastbus (ANSI/IEEE 960-1986, IEC 935), Futurebus (IEEE P896.x) and other modern high-performance buses. SC1 goals include a minimum bandwidth of 1 GByte/sec per processor in multiprocessor systems with thousands of processors; efficient support of a coherent distributed-cache ...

We describe the key role played by partial evaluation in the Supercomputer Toolkit, a parallel computing system for scientiic applications that eeectively exploits the vast amount of parallelism exposed by partial evaluation. The Supercomputer Toolkit parallel processor and its associated partial evaluation-based compiler have been used extensively by scientists at M.I.T., and have made possibl...