A system organized as a Hierarchy of Processor-And-Memory (HPAM) extends the familiar notion of memory hierarchy by including processors with diierent performance in diierent levels of the hierarchy. Tasks are assigned to diierent hierarchy levels according to their degree of parallelism. This paper studies the spatial locality (with respect to degree of parallelism) behavior of simulated paral...

In this paper we consider two problems: the edge coloring and the strong edge coloring problems on unit disk graphs (UDGs). Both problems have important applications in wireless sensor networks as they can be used to model link scheduling problems in such networks. It is well known that both problems are NP-complete, and approximation algorithms for them have been extensively studied under the ...

We speed up Neural Machine Translation (NMT) decoding by shrinking run-time target vocabulary. We experiment with two shrinking approaches: Locality Sensitive Hashing (LSH) and word alignments. Using the latter method, we get a 2x overall speed-up over a highly-optimized GPU implementation, without hurting BLEU. On certain low-resource language pairs, the same methods improve BLEU by 0.5 points...

this study was carried out to evaluate tobacco dust concentration and also designing a suitable ventilation system for reduction of tobacco dust concentration in a tobacco processing factory in the north of iran.gravimetric method was used to determine the tobacco dust concentrations in the emission sources an also indoor workplace. a local exhaust ventilation system was designed according to t...

This paper presents compilation techniques used to compress holes, which are caused by the nonunit alignment stride in a two-level data-processor mapping. Holes are the memory locations mapped by useless template cells. To fully utilize the memory space, memory holes should be removed. In a two-level data-processor mapping, there is a repetitive pattern for array elements mapped onto processors...

In this thesis, I describe the design and implementation of a software data cache for speculative loads in the SUDS (Software Undo System) runtime system. The basic functionality of this cache exploits short-term temporal locality and some spatial locality in the memory accesses of speculative processing elements. The cache implementation is also extended to exploit temporal locality of accesse...

The performance of the data cache in sharedmemory multiprocessors has been shown to be different from that in uniprocessors. In particular, cache miss rates in multiprocessors do not show the sharp drop typical of uniprocessors when the size of the cache block increases. The resulting high cache miss rate is a cause of concern, since it can significantly limit the performance of multiprocessors...