Progress in high-speed GaAs charge-coupled device (CCD) research is described. Experimental and modelling results are reported for two different structures; capacitive gate CCD's and resistive gate CCD's. A charge packet replicator/subtractor circuit is discussed.

This paper presents on-chip implementation of high speed low latency floating point adder /subtractor with high accuracy performance for FFT in OFDM transceiver. However due to high performance and high resolution, the floating point adder is matched with power network applications as well. The design was implemented for 32-bit pipelined adder/subtractor which satisfied IEEE-754 Standard for fl...

The biological deoxyribonucleic acid (DNA) strand has been increasingly seen as a promising computing unit. A new algorithm is formulated in this paper to design any DNA Boolean operator with molecular beacons (MBs) as its input. Boolean operators realized using the proposed design methodology is presented. The developed operators adopt a uniform representation for logical 0 and 1 for any Boole...

Feedback control is widely used in chemical engineering to improve the performance and robustness of chemical processes. Feedback controllers require a 'subtractor' that is able to compute the error between the process output and the reference signal. In the case of embedded biomolecular control circuits, subtractors designed using standard chemical reaction network theory can only realise one-...

Power dissipation has become an overriding concern for VLSI circuits and it may come to dominate the total chip power consumption as the technology feature size shrinks. The main aim of this paper is to minimize the leakage power by using a ultra low leakage techniques. In this work we are choosing the Benchmark circuit as full subtractor . This full subtractor are designed by using different t...

This paper proposes D4 FLMS-GSC algorithm interpreted as Daubechies D4 wavelet filter instead of subtractor filter which processes array antenna output. The structure of the proposed D4 FLMS-GSC algorithm has characteristic of reducing the computational requirement one-half compared to the FLMS-GSC algorithm. In addition, we obtain the MSE characteristics and adaptive beampattern of the D4 FLMS...

-In this paper a 4 bit parallel adder/subtractor circuit has been designed and analyzed. The circuit uses a controlled adder/subtractor circuit which converts the negative numbers into their 2’s complement. A comparative study of the silicon area and the power consumption has been done in the circuit using different channel lengths such as 65nm, 45nm. The circuit is designed and simulated using...

AbstractIn today’s world everyday a new technology which is faster, smaller and more complex than its predecessor is being developed. The increased number of transistors packed onto a chip of a conventional system results in increased power consumption that is why Reversible logic has drawn attention of Researchers due to its less heat dissipating characteristics. Reversible logic can be impose...

One of the most important tasks in design and manufacturing of integrated circuits is the testing phase. Distinguishing between faulty and fault free ICs is a difficult task Therefore, simulations are being done for different circuits to identify fault free and faulty circuits. The circuits include analog circuits, digital circuits &mixed signal circuits. Analog circuits like Low pass filter, H...

In this paper, we propose an efficient design of a reversible single precision floating point multiplier based on compressor. The single precision floating point multiplier requires the design of an efficient 24x24 bit integer multiplier. In the proposed architecture, the 24x24 bit multiplication operation is fragmented to nine parallel reversible 8x8 bit multiplication modules. In this paper, ...