Timing Closure in presence of long global wire interconnects is one of the main current issues in System-onChip design. One proposed solution to the Timing Closure problem is Latency-Insensitive Design (LID) [5,7]. It was noticed in [7] that, in many cases, the dynamically scheduled synchronisations introduced by latency-insensitive protocols could be computed off-line as a static periodic sche...

This report presents the Dafny language and verifier, with a focus on describing the main features of the language, including preand postconditions, assertions, loop invariants, termination metrics, quantifiers, predicates and frames. Examples of Dafny code are provided to illustrate the use of each feature, and an overview of how Dafny translates programming code into a mathematical proof of f...

A practical architecture, using a four-bar-linkage, is considered for the University of Minnesota direct drive rotot1. This statically-balanced direct drive robot has been constructed for stability analysis of the robot in constrained maneuvers.2-6 As a result of the elimination of the gravity forces (without any counter weights), smaller actuators and consequently smaller amplifiers were chose...

Current HDLs present a very low level of abstraction, often requiring the designer to work on details that could be hidden, and leaving little scope for synthesis tools to optimise performance. High-level hardware descriptions thus have a useful rôle in EDA, especially in areas such as rapid development, and reconfigurable computing using devices such as FPGAs. One approach to implementing thes...