We present the design of a high performance on-chip pipelined asynchronous DRAM suitable for use in a microprocessor cache. Although traditional DRAM structures suffer from long access latency and even longer cycle times, our design achieves a simulated core sub-nanosecond latency and a respectable cycle time of 4.8ns in a standard 0.25um logic process. We also show how the cycle time penalty c...

A recurring observation in memory industries is declining prices of about 60-70 percent within the first year of production of a new chip generation. Two reasons are made responsible for this pattern: (i) firms climb down a learning curve that induces declining prices, and (ii) firms that enter the product market first earn oligopoly rents. The objective of this paper is to decompose declining ...

The self-improvement of static random access memory (SRAM) cell stability by post-fabrication high-voltage stress is experimentally demonstrated and its mechanism is analyzed using 4k device-matrixarray (DMA) SRAM test element group (TEG). It is shown that the stability of unbalance cells is automatically improved by merely applying stress voltage to the VDD terminal of SRAM. It is newly found ...

Using reconfigurable, static random-access memory (SRAM) based field-programmable gate arrays (FPGAs) for space-based computation has been an exciting area of research for the past decade. In comparison with traditional radiation-hardened electronics, these devices would allow spacecrafts to be more adaptive and responsive to changing mission needs. Unfortunately, all commercially available SRA...

Testing static random access memories (SRAM’s) for all possible failures is not feasible. We have to restrict the class of faults to he considered. This restricted class is called a fault model. A fault model for SRAM’s is presented based on physical spot defects, which are modeled as local disturbances in the layout of an SRAM. Two linear test algorithms are proposed, that cover 100% of the fa...

Resistive Random Access Memory (RRAM)-based FPGA architectures employ RRAMs not only as memories to store the configuration but embed them in the datapaths of programmable routing resources to propagate signals with improved performances. Sources of power consumption have been intensively studied for conventional Static Random Access Memories (SRAM)-based FPGAs. However, very limited works focu...

Instability of SRAM memory cells derived from aggressive technology scaling has been recently one of the most significant issues. Although a 7T-SRAM cell with an area-tolerable separated read port improves read margins even at sub-1V, it unfortunately results in degradation of write margins. In order to assist the write operation, we address a new memory cell employing a look-ahead body-bias wh...

Custom memory organization are challenging task in the area of VLSI design. This study aims to design high speed and low power consumption memory for embedded system. Synchronous SRAM has been proposed and analyzed using various simulators. Xilinx simulator simulates the Synchronous SRAM memories which can perform efficient read/write capability for embedded systems. Xinix tool also provide the...

Physical and generic models that analytically couple the array architecture of CMOS SRAMs with the wire lengths and fan-outs along critical paths to decode and sense data are reported. Verified to be accurate with published SRAMs, these models enable the design of optimal array architectures to minimize total access time by balancing communication distance limited wire delays with fan-out and a...