This paper describes a prototype smart imager capable of adjusting the photo-integration time of multiple regions of interest concurrently, automatically and asynchronously with a single exposure period. The operation is supported by two interwined photo-diodes at pixel level and two digital registers at the periphery of the pixel matrix. These registers divide the focal-plane into independent ...

A major emerging challenge is how to protect people’s privacy as cameras and computer vision are increasingly integrated into our daily lives, including in smart devices inside homes. A potential solution is to capture and record just the minimum amount of information needed to perform a task of interest. In this paper, we propose a fully-coupled two-stream spatiotemporal architecture for relia...

In this paper, we propose a modified smart pixel mapping (MSPM) method for displaying orthoscopic three-dimensional (3D) images with a function of depth control in integral imaging system. In the proposed MSPM, the depth-converted elemental image array (EIA) is obtained through the pixel mapping process and the image interpolation technique. The proposed method gives us the depth conversion at ...

A 128 × 128 pixel functional image sensor was implemented. The sensor was able to capture images at 1,000 frame/s and extract the sizes and positions of 10 objects/frame when clocked at 8 MHz. The size of each pixel was 18 μm × 18 μm and the fill factor was 28%. The chip, 3.24 mm × 3.48 mm in size, was implemented with a 0.35 μm CMOS sensor process; the power consumption was 29.7 mW at 8 MHz. k...

Fast collection of three-dimensional (3D) data sets is required in a growing number of applications like robotic guidance, security and automotive. Scannerless Time-OfFlight (TOF) based active 3D vision systems are capable of collecting depth profiles of entire scenes in fraction of seconds but have the disadvantage of using high voltage and expensive electronic components. In this contribution...

We describe the chip design and system implementation of an optoelectronic parallel pipeline processing system composed of cascaded stages of smart pixel array cellular logic (SPARCL) processors interconnected with free-space digital optic channels. The SPARCL processing elements are arranged in a two-dimensional array, and each contains an independent optical input/output port and electrical n...

The optical components of a 64× 64 optoelectronic crossbar interconnect are described. The specifications and performance of the bulk, micro-optic, diffractive and thin-film components are discussed.

A new CMOS active pixel image sensor is reported. The sensor uses a 2.0 p n double-poly, double-metal foundry CMOS process and is realized as a 128 x 128 array of 40 p n x 40 pm pixels. The sensor features TTL compatible voltages, low noise and large dynamic range, and will be useful in machine vision and smart sensor applications.

The neu-MOS (vMOS) transistor is a new device that enables the design of conventional digital and analog circuits, in standard CMOS, with a factor of 5-10 decrease gate count. Furthermore, vMOS circuit characteristics are insensitive to transistor parameter variations but instead rely on coupling capacitor ratios. In this paper, we demonstrate this principle with results from fabricated control...

CMOS image sensors are a second-generation solid­ state imaging technology. CMOS active pixel sensors have performance competitive with CCD technology, and offer advantages in on-chip functionality, system power reduction, cost and miniaturization. CMOS VLSI circuits for imaging and readout, and on-chip integration of ADC and smart functions will be addressed.