In recent year’s reversible logic has been considered as an important issue for designing low power digital circuits. It has voluminous applications in the present rising nanotechnology such as DNA computing, Quantum Computing, low power VLSI and quantum dot automata. In this paper we have proposed optimized design of reversible sequential circuits in terms of number of gates, delay and hardwar...

We suggest the use of a declarative programming language to design and describe circuits, concentrating on the use of higher-order functions to structure and simplify designs. In order to describe sequential circuits, we use a language , fp, which abstracts from temporal iteration. The practicalities of vlsi design make regularity attractive, and we describe the use of familiar higher order fun...

The reliability and the cost of electronic circuits are closely connected to the maximum power dissipated by them. Tools for evaluating the worst case power consumption of sequential circuits is becoming a primal concern for designers of low-power circuits. In the paper the task of estimation of peak sustainable power for CMOS synchronous sequential circuit is considered when its automaton desc...

Activity in Sequential Logic Circuits Jos e Monteiro, Srinivas Devadas Department of EECS, MIT, Cambridge Bill Lin IMEC, Leuven Abstract We describe a computationally e cient scheme to approximate average switching activity in sequential circuits which requires the solution of a non-linear system of equations of size N , where the variables correspond to state line probabilities. We show that t...

This paper describes a method of identifying a set of crosstalk-induced delay faults which may need to be tested in synchronous sequential circuits. In this process, the false crosstalk-induced delay faults that need not (and/or can not) be tested in synchronous sequential circuits are also identify. Our method classifies the pairs of aggressor and victim lines, using topological information an...

This paper presents a new approach to Automatic Test Pattern Generation for sequential circuits. Traditional topological algorithms nowadays are able to deal with very large circuits, but often fail when highly sequential subnetworks are found. On the other hand, symbolic techniques based on Binary Decision Diagrams proved themselves very efficient on small or medium circuits, no matter their s...