A fast fault simulation approach based on ordinary logic emulation is proposed. The circuit configured into our system that emulates the faulty circuit’s behavior is synthesized from the good circuit and the given fault list in a novel way. Fault injection is made easy by shifting the content of a fault injection scan chain or by selecting the output of a parallel fault injection selector, with...

Alloy uses a first-order relational logic for modeling designs. The Alloy Analyzer translates Alloy formulas for a given scope, i.e., a bound on the universe of discourse, to Boolean formulas in conjunctive normal form (CNF), and subsequently checks them using propositional satisfiability solvers. We present SERA, a novel algorithm that compiles a relational logic formula for a given scope to a...

Reversible logic has come to the forefront of theoretical and applied research today. Although many researchers are investigating techniques to synthesize reversible combinational logic, there is little work in the area of sequential reversible logic. Latches and flip-flops are the most significant memory elements for the forthcoming sequential memory elements. In this paper, we proposed two ne...

A new method for state justiication is proposed for sequential circuit test generation. The linear list of states dynamically obtained during the derivation of test vectors is used to guide the search during state justiication. State-transfer sequences may already be known that drive the circuit from the current state to the target state. Otherwise, genetic engineering of existing state-transfe...

Low power design is most required now a days due to scaling down the technology where minimizing the voltage level is the most effective way to minimize the power consumption. This paper presents a double pulse flip flop implemented using 0.18 μm technology. The proposed flip flop avoids unnecessary switching and stacking of transistors and thus consume less power as compared to conventional fl...

& Conclusion| We propose a sequential probability ratio test based on a two parameter Weibull distribution for IC failure analysis. The shape parameter of the Weibull distribution characterizes the decreasing, constant and the increasing failure rate regions in the bath tub model for ICs. The algorithm detects the operating region of the IC based on the observed failure times. Unlike the xed-le...

The temporal logic model checking algorithm of Clarke, Emerson, and Sistla [17] is modified to represent state graphs using binary decision diagrams (BDD’s) [7] and partitioned trunsirion relations [lo], 1111. Because this representation captures some of the regularity in the state space of circuits with data path logic, we are able to verify circuits with an extremely large number of states. W...

Reducing Power dissipation is one of the crucial problems in today’s scenario. So this dissipation has become a bottleneck in the design of high speed synchronous systems which are operating at high frequency. Clock signals have been a great source of Power. Design can be made on the basis of Clock gating approach to reduce the consumption of clock’s signal switching power which is the foremost...

Reversible circuits for SR ip op, JK ip op, D ip op, T ip op, Master Slave D ip op and Master Slave JK ip op have been provided with three di erent logical approaches. All the circuits have been optimized with the help of existing local optimization algorithms (e.g. template matching, moving rule and deletion rule) and the optimized sequential circuits have been compared with the earlier propos...

Reversible sequential circuits are going to be the significant memory blocks for the forthcoming computing devices for their ultra low power consumption. Therefore design of various types of latches has been considered a major objective for the researchers quite a long time. In this paper we proposed efficient design of reversible sequential circuits that are optimized in terms of quantum cost,...