This paper proposes a review on Partial reconfiguration using Field Programmable Gate Array (FPGA). By downloading configuration bit files Partial Dynamic Reconfiguration (PDR) dynamically modifies the hardware portion of the device. Both FPGA and reconfigurable are used to speed up the performance of various applications. This makes the FPGA to be used in new dimension with an advantage of mor...

this paper presents a new hybrid method for optimal multi-objective reconfiguration in a distribution feeder in addition to determining the optimal size and location of multiple-distributed generation (dg). the purposes of this research are mitigation of losses, improving the voltage profile and equalizing the feeder load balancing in distribution systems. to reduce the search space, the improv...

Modular systems implemented on field-programmable gate arrays (FPGAs) can benefit from being able to load and unload modules at run-time, a concept that is of much interest in the research community. Although dynamic partial reconfiguration is possible in Virtex and Spartan series FPGAs, the configuration architecture of these devices is not amenable to modular reconfiguration, a limitation whi...

configuration assuring the required properties if the optimal system reached. 3. RECONFIGURATION METHODS In this paper the transient properties of reconfigurable IIR filters are investigated using theoretical analysis and simulations. First the structure dependency of the one-step reconfiguration transients is proved, and some suitable filter structures are characterised. Next to reduce transie...

The limited I/O bandwidth in reconfigurable devices results in a prohibitively high reconfiguration overhead for dynamically reconfigured FPGA-based platforms. Thus, the full potential of dynamic reconfiguration can not be exploited. Usually, any attainable speed-up by executing an application on hardware is diminished by the reconfiguration overhead. The self-reconfiguration concept aims at dr...

Dynamic Partial Reconfiguration(DPR) optimizes the resource utilization in the Field Programmable Gate Array(FPGA) over time and space nowadays. But the lack of standard tools and interface makes the extensive application of DPR rather difficult . With the open source Linux widely used in the Xilinx Zynq, users’ demand for the reconfiguration becomes urgent. Linux-based dynamic partial reconfig...

Dynamic Circuit Specialization is used to optimize the implementation of a parameterized application on an FPGA. Instead of implementing the parameters as regular inputs, in the DCS approach these inputs are implemented as constants. When the parameter values change, the design is reoptimized for the new constant values by reconfiguring the FPGA. This allows faster and more resource-efficient i...

In interconnection networks, reconfiguration protocol is necessary to remap and reconnect the network paths, so that the network remains connected. However, the reconfiguration process brings the deadlock problem and prevention of deadlock is a tedious task in this situation. In existing works, very little work have considered deadlock problem and further, they paid no attention to reduce packe...