A formal methodology for automatic hardwaresoftware partitioning and co-scheduling the tasks of an application between Microprocessor and Programmable Logic Devices (PLDs) has become emerging research area of hardware software co-design. The main objective of this research is to get full advantage of hardware utilization and speedup the application execution. Hardware software partitioning and ...

Reconfigurable computing systems allow executing tasks in a true multitasking manner. Such systems share the reconfigurable device and processing unit as computing resources which leads to highly dynamic allocation situations. To manage such systems at runtime, a reconfigurable operating system is needed. The main part of this operating system is resource management unit which performs HW/SW pa...

Remote Monitor & Control systems are increasingly being used in security, transportation, manufacturing, supply chain, healthcare, biomedical, chemical engineering, etc. In this research, attempt is to develop a solution of wireless monitoring and control for such industrial scenarios. The solution is built on two components – a generic wireless interface for remote data collection/actuation un...

Certain numerical computations benefit from dedicated computation units, e.g. providing increased computation accuracy. Exploiting current interconnection technologies and advances in reconfigurable logic, restrictions and drawbacks of past approaches towards application-specific units can be overcome. This paper presents our implementation of an FPGA-based hardware unit for exact arithmetics. ...

We demonstrate reconfigurable anisotropic metamaterials at terahertz frequencies where artificial "atoms" reorient within unit cells in response to an external stimulus. This is accomplished by fabricating planar arrays of split ring resonators on bimaterial cantilevers designed to bend out of plane in response to a thermal stimulus. We observe a marked tunability of the electric and magnetic r...

This paper presents an implementation of an Advanced Encryption Standard (AES) encryption unit using dynamic reconfiguration based on the Xilinx Spartan-3 FPGA platform. The proposed design reuses resource of FPGA by adapting dynamic reconfiguration to reduce the number of resource used in the circuit. By changing circuits at runtime, the size of the whole circuit is limited to the largest reco...

In this paper, we propose a method for speeding-up Digital Signal Processing applications by partitioning them between the reconfigurable hardware blocks of different granularity and mapping critical parts of applications on coarse-grain reconfigurable hardware. The reconfigurable hardware blocks are embedded in a heterogeneous reconfigurable system architecture. The fine-grain part is implemen...

ÐThis paper introduces MorphoSys, a reconfigurable computing system developed to investigate the effectiveness of combining reconfigurable hardware with general-purpose processors for word-level, computation-intensive applications. MorphoSys is a coarse-grain, integrated, and reconfigurable system-on-chip, targeted at high-throughput and data-parallel applications. It is comprised of a reconfig...

Reconfigurable computing has become a hot topic in research due to its high-performance and flexibility. In this paper we present a simulator called JRSim for mesh-based reconfigurable architectures. The purpose of this simulator is to provide a platform to evaluate new architectures, and to assist in analysis of algorithms as well as the visualization of their behavior. JRSim is a platform-ind...

New computer architectures are being proposed and will be implanted in the next few years. A common trend to improve the system performance is to include some reconfigurable logic components into future multi-core chips. Several prototypes already exist but there still is a lack of support from the programming models, the compilers and the operating system. Reconfigurable architectures enable a...