A new watchdog processor scheme for concurrent checking of program control flow is presented. This method is intended to check state of the art processor architectures with on-chip caches as building blocks of multiprocessor systems. The signatures are assigned, so that the processor instruction bus needs not be monitored. The run-time and reference signatures are embedded into the checked prog...

In this paper, we first discuss the need for network processors. Consequently, relying on a “program to program” communications model, we briefly describe the functions that are found in the seven OSI layers and classify them using functional requirement criteria for a network processor. Subsequently, we summarize the current state of the art commercially developed network processors. Based on ...

Aggressive program optimization requires accurate profile information, but such accuracy requires many samples to be collected. We explore a novel profiling architecture that reduces the overhead of collecting each sample by including a programmable co-processor that analyzes a stream of profile samples generated by a microprocessor. From this stream of samples, the co-processor can detect corr...

In digital signal processing, bit width of intermediate variables should be longer than that of input and output variables in order to execute intermediate operations with high precision. Then a processor core for digital signal processing is required to have two types of register files, one of which is used by input and output variables and the other one is used by intermediate variables. This...

In this paper we describe a methodology for the formal verification using theorem proving of a DSP processor chip. We specified both the behavioral and implementation (at the register level) of the processor. Then we create a new representation of the processor such that its complexity can be handled by the theorem prover. Finally, we make a proof of the full instruction set of this processor. ...

In a large class of embedded systems, dynamic multithreading using traditional OS techniques is infeasible due to memory and processing overheads or lack of operating systems (OS) availability for the target embedded processor. In this work, we propose a source-to-source translator that takes a POSIX compliant multithreaded C program as input and generates an equivalent, embedded processor inde...

Estimating the Worst-case Execution Time (WCET) of real-time embedded software is an important problem. WCET is defined as the upper bound b on the execution time of a program P on a processor X such that for any input the execution time of P on X is guaranteed to not exceed b. Such WCET estimates are crucial for schedulability analysis of real-time systems. In this paper, we present Chronos, a...

This paper deals with two-processor scheduling for a class of program nets, that are acyclic and SWITCH-less, and of which each node has unity node firing time. Firstly, we introduce a hybrid priority list L∗ that generates optimal schedules for the nets whose AND-nodes possess at most single input edge. Then we extend L∗ to suit for general program nets to give a new priority list L∗∗. Finally...

SPMD Single Program Multiple Data models and other traditional models of data parallelism provide parallelism at the processor level Barrier synchroniza tion is de ned at the level of processors where when a processor arrives at the barrier point early and waits for others to arrive no other useful work is done on that processor Program restructuring is one way of min imizing such latencies How...