This paper presents two new general threshold gate (GTG) structures which are based on the monostable-bistable element (MOBILE) as their main part. These new GTGs eliminate an RTD from the structure compared to old structures and lead to less elements count and better performance in terms of power consumption, maximum frequency, and power-delay product (PDP). In the paper also two new single ga...

In this paper, we present an efficient architecture for the implementation of a delayed least mean square Adaptive filter. For achieving lower adaptation-delay and area-delay-power, we use a novel partial product generator and propose an optimized balanced pipelining across the time-consuming combinational blocks of the structure.We propose an efficient fixed-point implementation scheme in the ...

Power efficiency is becoming an increasingly important design aspect for FPGAs. Recently it has been shown that well-known power minimization techniques in the ASICs such as creating supply voltage (Vdd) scalable islands of different granularity can be applied to FPGAs. However, the discrete routing architecture of FPGAs amplifies any constraint imposed on the placement stage. In this work, we ...

This research paper presents highly optimized barrel shifter at 22nm Hi K metal gate strained Si technology node. This barrel shifter is having a unique combination of static and dynamic body bias which gives lowest power delay product. This power delay product is compared with the same circuit at same technology node with static forward biasing at ‘supply/2’ and also with normal reverse substr...

The power-delay product is a direct measurement of the energy expanded per operational cycle of an arithmetic circuit. Lowering the supply voltage of the full adder cell to achieve low power-delay product is a sensible approach to improve the power efficiency at sustainable speed of arithmetic circuits composed of such instances at high level design. In this paper, a novel design of a low power...

Adders, as one of the major components of digital computing systems, have a strong influence on their performance. There are various types of adders, each of which uses a different algorithm to do addition with a certain delay. In addition to low computational delay, minimizing power consumption is also a main priority in adder circuit design. In this paper, the proposed adder is divided into s...

A Fault tolerant reversible logic has gained importance as they consume low power and less heat dissipation. The benefits of logical reversibility can be gained only after employing physical reversibility. Every future technology will have to use reversible gates in order to reduce power. This paper proposed a new fault tolerant reversible 4*4 RR-gate which satisfies the reversible and parity p...

In the FIR filter design the MCM block optimization plays a vital role to reduce the critical path which is due to the product accumulation section. The critical path delay is reduced by using the Transposed direct form (TDF) FIR filter is proposed. The filters which have large number of multipliers. The partial products by using OTFC-LRRS multiplier is implemented in the FIR filter. The array ...