An optical hybrid design based on paired multimode interference couplers in silicon-on-insulator process is investigated. The device exhibits greater than 20 dB CMRR and low phase deviation (<10) over 30 nm in the C-band. The design eliminates the use of optical cross waveguides for integration with balanced photodetectors. Introduction Coherent detection scheme provides high spectral efficienc...

VLSI technology is being driven to giga-scale levels of integration with IC minimum feature dimensions approaching atomic scales. System-level integration is now pursued as critical in major commercial applications including wireless communication, computing, and multimedia. On-chip signal integrity, noise, and electromagnetic compliance (EMC) are becoming “showstoppers” in addition to escalati...

Thermal impedance is required to describe static and fast dynamic thermal behavior in silicon-on-insulator (SOI) devices. This study presents an empirical physical model, which accounts for gate length, calculating the of multi-finger partially depleted (PD) SOI MOSFETs at room temperature. For first time, parameters model are obtained from measurements ac conductance characteristic frequency d...

This work presents a technique for reducing the total leakage current in PD-SOI combinational circuits by mixing floating-body and tied-body transistors in the same circuit. Basic gate characterization data are first presented, and then used as part of a static timing analysis based optimization algorithm. Results obtained from a number of benchmark circuits show a decrease of up to 86% in tota...

The interaction of the body bias effect, device size, and analog characteristics such as DC gain, the matching effect, and speed (fT and fmax) of the sub-0.2 lm PD-SOI technology is reported. From the study, the optimized device size and the body bias for the analog and radio-frequency applications can be determined according to the specific utilization of the chip. 2002 Published by Elsevier S...

Recently a uni-traveling carrier photodetector (UTC-PD) with a 3 dB bandwidth beyond 67 GHz was presented [1]. The device shows good performance up to 3 mA of photocurrent but experiences thermal failure (see Fig. 1a) at higher currents due to the poor heat extraction in membrane-type devices. Improvements to the thermal design are proposed that promise to double the possible photocurrent befor...

In this paper, generation-type drain current transients, in advanced (down to 50nm gate-length) floating-body PD SOI MOSFETs are investigated by 2D numerical simulation in weak inversion operation. An original compact analytical model is derived for the pure transient weak inversion operation and validated on both elementary and realistic 2D structures. The proposed sub-threshold transient comp...

In this work, a novel Silicon on Insulator (SOI) MOSFET is proposed and investigated. The drain and source electrode structures are optimized to enhance ON-current while global device temperature and hot carrier injection are decreased. In addition, to create an effective heat passage from channel to outside of the device, a silicon region has embedded in the buried oxide. In order to reduce th...

In this paper, underlap channel dopant-segregated Schottky barrier (DSSB) SOI MOSFET has been proposed, in which the increased effective channel length (Leff) due to underlap channel at both source/drain (S/D) sides reduces the leakage currents, short-channel effects and the parasitic capacitances as compared to overlap channel DSSB SOI MOSFET. Although in strong inversion the voltage drop acro...