High-speed 64-bit binary comparator using three stages with CMOS logic style is proposed in this brief. Comparison is most basic arithmetic operation that determines if one number is greater than, equal to, or less than the other number. Comparator is most fundamental component that performs comparison operation. This brief presents comparison of modified and existing 64-bit binary comparator d...

The design of high gain, wide dynamic range op-amps for switched-capacitor circuits has become increasingly challenging with the migration of designs to scaled CMOS technologies. The reduced power supply voltages and the low intrinsic device gain in scaled technologies offset some of the benefits of the reduced device parasitics. An alternative comparator-based switched-capacitor circuit (CBSC)...

quantum-dot cellular automata (qca) is an emerging and promising technology that provides significant improvements over cmos. recently qca has been advocated as an applicant for implementing reversible circuits. however qca, like other nanotechnologies, suffers from a high fault rate. the main purpose of this paper is to develop a fault tolerant model of qca circuits by redundancy in hardware a...

The need for low power, high speed Analog-To-Digital converters is pushing towards the use of dynamic comparator to maximize speed &power efficiency. In this paper, we designed a Dynamic Latched Double-Tail Comparator which is used in implementation of many ADC’s. An analysis on the delay of the comparator will presented. Simulation results in 0.18um CMOS technology confirm the analysis results...

A CMOS current comparator with well-controlled hysteresis is described. The current comparator allows bidirectional input currents. Expcrimental results show that the current comparator takes approximately 300 ns to rcsolve a 2 KA difference of input and threshold currents.

This paper explores various available comparator designs and proposes an improved ultra low power comparator with reduced delay at 90nm. Dynamic comparators which are extensively used in data converters and digital signal processors require low power consumption and high speed. A clock based dynamic comparator is simulated with delay of 64ps and power dissipation of 31.8μW. The comparator struc...

A high-speed 64-bit binary comparator is proposed in this brief. Comparison is most basic arithmetic operation that determines if one number is greater than, equal to, or less than the other number. Comparator is most fundamental component that performs comparison operation. This brief presents comparison of modified and existing 64-bit binary comparator designs concentrating on delay. Means so...

In this paper a new design of comparator is described with the help of Full adder which are the basic building block of ALU and ALU is a basic functioning unit of the microprocessors and DSP. In the world of technology it has become essential to develop various new design methodologies to reduce the power and area consumption. In this paper comparator are developed using various design of full ...

This paper presents a new low power 2-Bit magnitude comparator using full adder technique. The proposed magnitude comparator (PTL logic) has been compared with existing magnitude comparator (GDI technique). The performance analysis of both magnitude comparators is done on basis of power consumption with respect to input voltage, temperature, and frequency; using Tanner EDA tool version 12.6 at ...

Dynamic comparators are popular structures used in analog circuits such as RFID tags, ADC, memory modules, etc. Compared with traditional open-loop amplifiers that can be used as a comparator, well-designed dynamic comparators are usually faster and more powerefficient, but dynamic CMPs also have some problems. Device mismatch-induced offset voltages is a major challenge when designing dynamic ...