A comprehensive study of the intrinsic reliability of a 1.4-nm (equivalent oxide thickness) JVD Si3N4 gate dielectric subjected to constant-voltage stress has been conducted. The stress leads to the generation of defects in the dielectric. As the result, the degradation in the threshold voltage, subthreshold swing, gate leakage current, and channel mobility has been observed. The change in each...

We report on the defect generation under constant voltage stress in La2O3/HfO2 gate stacks grown on Germanium (001) substrates by molecular beam deposition utilizing a stress and sense technique. A voltage range from 0.5V up to 2.4V was used for the measurements. At low applied gate voltages, the stress induced current decrease could be explained by a field lowering model due to charge trapping...

A new output structure for class E power amplifier (PA) is proposed in this paper. A series LC resonator circuit, tuned near the second harmonic of the operating frequency is added to the output circuit. This resonator causes low impedance at the second harmonic. The output circuit is designed to shape the switch voltage of the class E amplifier and lower the voltage stress of the transistor. T...

In this paper, a new high efficiency, high step-up, non-isolated, interleaved DC-DC converter for renewable energy applications is presented. In the suggested topology, two modified step-up KY converters are interleaved to obtain a high conversion ratio without the use of coupled inductors. In comparison with the conventional interleaved DC-DC converters such as boost, buck-boost, SEPIC, ZETA a...

The boost topology is often the designer's first choice when dealing with PFC front-ends. This topology is well documented in the literature and has obvious advantages like continuous input current and low voltageand current-stress compared to other PFC topologies. The PFC SEPIC converter also has the advantage of the continuous input current but suffers from high voltageand current stress. In ...

in this paper are present the results of measurements of magnetic induction at some locationsin city bor (the east serbia) dating from the household electric devices and transformer stations suited near the residental areas. stress is on the extremely low frequent electromagnetic radiation from transformer stations and other high voltage instalations in urban areas. risk of the extremely low fr...

This paper presents a sample-and-hold circuit based on a novel implementation of the bootstrapped low-voltage analog CMOS switch. The heart of this circuit is a new low-voltage and low-stress CMOS clock voltage doubler. Through the use of a dummy switch, the charge injection induced by the bootstrapped switch is greatly reduced resulting in improved sample-and-hold accuracy. Simulation results ...

This paper presents the design and preliminary results of a full differential sample-and-hold circuit based on the "flipped voltage follower" (FVF) cell. The heart of this circuit is a fully differential low-voltage OTA based on FVF technique. The use of the FVF reduces the supply power requirements in the OTA. To overcome input sampling switches limitation imposed by the low supply voltage we ...