iii ACKNOWLEDGEMENTS I would like to express my sincere gratitude and appreciation to everyone who has helped to make this thesis possible. I would like to deliver my special thanks to my wife and my parents for their love, support, and patience. My deep appreciation also goes to Alfred Andrew for their time and valuable suggestions. Finally, I owe gratitude to all of my friends and colleagues ...

An effective dynamical description of a general class of stochastic phase oscillators is presented. For this, the effective phase velocity is defined either by the stochastic phase oscillators invariant probability density or its first passage times. Using the first approach the effective phase exhibits the correct frequency and invariant distribution density, whereas the second approach models...

High-speed links which employ source synchronous clocking architectures have the ability to track correlated jitter between clock and data channels up to high frequencies. However, system timing margins are degraded by channel skew between clock and data signals and high-frequency loss. This paper describes how these key channel effects impact the jitter performance and influence the clocking a...

A 0.5–5 GHz wide-range multiphase delay-locked loop (MDLL) with a calibrated charge pump is presented. A multiperiod-locked technique is used to enhance the input frequency range of a MDLL and avoid the harmonic-locked problem. The charge pump current is also calibrated to reduce the static phase error. This MDLL has been fabricated in 0.13m CMOS process. The measured root-mean-square and peak-...

A high-speed triangular-modulated spread-spectrum clock generator using a fractional phase-locked loop is presented. The fractional division is implemented by a nested fractional topology, which is constructed from a dual-modulus divide-by-(N–1/16)/N divider to divide the VCO outputs as a first division period and a fractional control circuit to establish a second division period to cause the o...

This work concerns with the design and analysis of phase locked loops (PLLs). In the last decade a lot of works have been done about the analysis of PLLs. The phase locked loops are analyzed briefly, second order, third order, and fourth order. In practically the design of 1.3 GHz, 1.9V second order PLL is considered. SPICE simulation program results confirm the theory. Key-Words: Phase Locked ...

This paper presents a low-complexity real-time single-tone phase and frequency estimation technique based on zero-crossing detection and linear regression. The proposed zerocrossing phase and frequency estimator fills a gap between lowcomplexity phase locked loop estimation and high-performance maximum likelihood estimation. Similar to a phase locked loop, the zero-crossing phase and frequency ...

Frequency synthesis is one of the most important and most actively researched subjects in the field of VLSI mixed-signal circuit design. Among the existing techniques in this area, phase locked loop fractional architecture is a widely used one for generating frequencies which are not integer multiple of the input reference frequency. Flying-Adder architecture is an emerging technique which is b...