An analytical compact model for the asymmetric lightly doped Double Gate (DG) MOSFET is presented. The model is developed using the Lambert Function and a 2-dimensional (2-D) parabolic electrostatic potential approximation. Compact models of the net charge and channel current of the DGMOSFET are derived in section 2. Results for the channel potential and current are compared with 2-D numerical ...

Aguilar-Sanjuan et al., (2021). LDDS: Python package for computing and visualizing Lagrangian Descriptors Dynamical Systems. Journal of Open Source Software, 6(65), 3482, https://doi.org/10.21105/joss.03482

Besides common implant techniques, dopant diffusion enables steep diffusion profiles in heavily doped deep-source drain and ultra-shallow junctions as required in advanced microelectronic technology. Experimental phosphorus dopant diffusion profiles in silicon are described by a rational function diffusion (RFD) model, based on direct solution of Fick’s equations and suitable for actual work in...

Double gate MOSFET is widely used for sub-50nm technology of transistor design .They have immunity to short channel effects, reduced leakage current and high scaling potential. The single gate Silicon–on-insulator (SOI) devices give improved circuit speed and power consumption .But as the transistor size is reduced the close proximity between source and drain reduces the ability of the gate ele...

A closed-form inversion charge-based long-channel drain current model is developed for a symmetrically driven, lightly doped Symmetric Double-Gate MOSFET (SDGFET). It is based on the drift-diffusion transport mechanism and considers velocity saturation using the Caughey-Thomas model with exponent n=2, vertical field mobility degradation and body doping. It is valid in subthreshold as well as ab...

We present the two-dimensional optimization of the acceptor doping profile of a 0.25 /im MOSFET which improves the drive current by 48% compared to a uniformly doped device delivering the same drain-source leakage current. Various values for the supply voltage and the allowed leakage current are used to qualitatively investigate their influence on the optimal profile.

We have profiled the parasitic source and drain resistances versus current in recessed-gate HFET's with heavily-doped caps, using an InAIAs/n+-InP HFET as a vehicle. We observe a dramatic reduction in the parasitic resistances at moderate-to-high currents as significant current passes through the cap. Consequently, we note very little dependence in gm on the length of the extrinsic gate-source ...

The fabrication of ordered arrays of nanoporous Si nanopillars with and without nanoporous base and ordered arrays of Si nanopillars with nanoporous shells are presented. The fabrication route is using a combination of substrate conformal imprint lithography and metal-assisted chemical etching. The metal-assisted chemical etching is performed in solutions with different [HF]/[H2O2 + HF] ratios....