In testing certain systems, checking for burst errors is important. This is due to the fact that errors are confined to a certain number of bits. If signature analysis is used to test a circuit then the testing capabilities depend on the polynomial that defines the linear feedback shift register (LFSR) used in the test. In this paper we show that the LFSR that is suitable for checking for burst...

We present a realization of an LFSM that utilizes an LFSR. This is based on a well-known fact from linear algebra. This structure is used to show that a previous attempt at using a CA in place of an LFSR in constructing a stream cipher did not necessarily increase its security. We also give a general method for checking whether or not a nonlinear filter generator based on an LFSM allows reducti...

A new side channel attack against a simple LFSR is presented. The proposed attack targets a single Galois LFSR running on an embedded device where the only accessible information is the side channel leakage. Even if it is made only of simple XOR gates, such an object is vulnerable to side channel cryptanalysis depending on its implementation. Our attack combines simple side channel analysis and...

This paper describes some attacks on word-oriented stream ciphers that use a linear feedback shift register (LFSR) and a non-linear lter. These attacks rely on exploiting linear relationships corresponding to multiples of the connection polynomial that de ne the LFSR.

A new lossless test vector compressionn scheme is presentedd whichh combines linear feedback shift register (LFSR) reseedingg andd statistical codingg inn aa powerful way. Test vectors cann be encodedd as LFSR seeds by solvingg aa system of linear equations. The solutionn space of the linear equations cann be quite large. The proposedd methodd takes advantage of this large solutionn space too f...

One of the major cipher symmetric algorithms is AES. Its main feature is to use S-BOX step, which is the only non-linear part of this standard possessing fixed structure. During the previous studies, it was shown that AES standard security was increased by changing the design concepts of S-BOX and production of dynamic S-BOX. In this paper, a change of AES standard security is studied by produc...

The design for low power has become one of the greatest challenges in high-performance very large scale integration (VLSI) design. It has been found that the power consumed during test mode operation is often much higher than during normal mode operation. This is because most of the consumed power results from the switching activity in the nodes of the circuit under test (CUT), which is much hi...

Pseudo-random testing is popularly used, particularly in Built-In Self Test (BIST) applications. To achieve a desired fault coverage, pseudo-random patterns are often supplemented with few deterministic patterns. When positions of deterministic patterns in the pseudo-random sequence are known a priori, pseudo-random sub-sequences can be chosen such that they cover these deterministic patterns. ...

A new hybrid BIST scheme is proposed which is based on using an “incrementally guided LFSR.” It very efficiently combines external deterministic data from the tester with on-chip pseudo-random BIST. The hardware overhead is very small as a conventional STUMPS architecture [1] is used with only a small modification to the feedback of the LFSR which allows the tester to incrementally guide the LF...

New mathematical techniques for analysis of raw dumps of NAND flash memory were developed. These techniques are aimed at detecting, by analysis of the raw NAND flash dump only, the use of LFSR-based scrambling and the use of a binary cyclic code for errorcorrection. If detected, parameter values for both LFSR and cyclic error-correcting code are determined simultaneously. These can subsequently...