Designing a modern microprocessor is a complex task that demands careful balance between cycle time, cycles-per-instruction, and area costs. In particular, the instruction fetch unit greatly affects the performance of a multi-issue processor. It must provide adequate bandwidth to sustain peak instruction issue rate, and must predict future instruction sequences with high accuracy. In the UltraS...

This paper presents the results of a quantitative evaluation of the instruction fetch characteristics for media processing. It is commonly known that multimedia applications typically exhibit a significant degree of processing regularity. Prior studies have examined this processing regularity and qualitatively noted that in contrast with general-purpose applications, which tend to retain their ...

In a dynamic reordering superscalar processor, the front-end fetches instructions and places them in the issue queue. Instructions are then issued by the back-end execution core. Till recently, the front-end was designed to maximize performance without considering energy consumption. The front-end fetches instructions as fast as it can until it is stalled by a filled issue queue or some other b...

Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works, must be obtained from the Abstract In conventional processors, each instruction cache fetch brings in a ...

Modern computer architectures represent design tradeoffs involving a large number of variables in a very large design space. Choices related to organization of major system blocks (CPU, cache, memory, I/O) do not work well across different applications. The performance and power variation across applications and against changing data set in a given application can easily be an order of magnitud...

Filter cache has been proposed as an energy saving architectural feature [9]. A filter cache is placed between the CPU and the instruction cache (I-cache) to provide the instruction stream. Energy savings result from accesses to a small cache. There is however loss of performance when instructions are not found in the filter cache. The majority of the energy savings from the filter cache in hig...

The implementation of modern high performance computer is increasingly directed toward parallelism in the hardware. However, most of the current fetch units are limited to one branch prediction per cycle and therefore, can fetch no more than one basic block per cycle. While fetching a single basic block each cycle is sufficient for implementations that issue small number of instructions per cyc...

In SMT processors several threads run simultaneously to increase available ILP, sharing but competing for resources. The instruction fetch policy plays a key role, determining how shared resources are allocated. When a thread experiences an L2 miss, critical resources can be monopolized for a long time choking the execution of the remaining threads. A primary task of the instruction fetch polic...

VLSI devices with high power demands have several important drawbacks; power to run the chip must be supplied externally, and power is dissipated as heat, which must be removed from the circuit. Processor architects tend to view these issues as circuit technology or packaging problems. However, these solutions are limited, and do not necessarily provide insight into more direct approaches to en...

Multiple-block prediction is emerging as a new and exciting research area. Highly accurate multiple-block predictors are essential for wide instruction fetch mechanisms, that will support future generations of microprocessors. The block-based trace cache is a recent proposal for wide instruction fetch. It aligns and stores instructions at the basic block level instead of at the trace level, thu...