This paper describes a new and eeective approach to register and interconnect optimisation, which is applicable in a dual context : to reduce chip area in high-level synthesis, and to reduce resource load (and thus execution time) in retargetable code generation. The key idea is to carefully optimise the way in which data is transferred between functional units. The impact on high-level synthes...

The scheduling problem — one of the central tasks in high-level synthesis — is the problem of determining the order in which the operations in the behavioral description will execute. This tutorial introduces the scheduling problem, and describes four scheduling algorithms commonly used today to solve those problems.

| This paper describes a novel approach to high-level synthesis of arbitrarily complex pipelined circuits, including pipelined circuits with feedback, and the synthesis algorithm that makes the approach viable in practice. Our approach provides a high-level, modular speciication language with an eecient implementation. In our system, the designer speciies the circuit as a set of independent mod...

T/ie paper describes objcctives of high-level synthesis. It concentrates on operation scheduling strategies and thc interaction with the resource allocation. Some transformational and iterative/constructive scheduling algorithms are described. Moreover, a new scheduling/alhcation approach is prcsented and compared with other known algorithms. Finally, some open problems of the high-levcl synthe...

The earlier the stage where we perform low power design, the higher the dynamic power reduction we achieve. In this paper, we focus on reducing switching activity in high-level synthesis, especially, in the problem of functional module binding, bus binding or register binding. We propose an effective low power bus binding algorithm based on the table decomposition method, to reduce switching ac...

In this paper, we will describe how a complete graphics processing pipeline was implemented using an HLS methodology. As with most real-life applications, this design consists of a complex mix of control logic, datapaths, interfaces, and hierarchy. We will show how these four essential ingredients are addressed in the context of HLS, and we will review the capabilities of current-generation HLS...

In this paper, we present a first approach for array-level energy estimation during high-level synthesis when mapping piecewise regular algorithms onto massively parallel full size processor arrays. Innately, piecewise regular algorithms have some power consumption friendly properties, e.g., they may be mapped onto processor arrays with only local interconnect and memory. In addition to these p...

A known problem in the area of hardware/software codesign is the selection of the proper interface between the different parts of the design. This paper presents a technique which eases the selection by combining different synthesis techniques together with rapid prototyping. Application field of the technique is the design of communication systems where C and VHDL are generated from a specific...

This paper presents a methodology for high-level synthesis of continuous-time linear analog systems. Synthesis results are architectures of op-amps, sized resistors and capacitors such that their ac behavior and total silicon area are optimized. Bounds for op-amp dc gain, unity-gain frequency, input, and output impedances are found as a byproduct of synthesis. Subsequently, a circuit synthesis ...

This paper describes optimization techniques using don't-care conditions that span the domain of highlevel and logic synthesis. The following three issues are discussed: 1) how to describe and extract don't-care conditions from high-level descriptions; 2) how to pass don't-care conditions from high-level to logic synthesis; and 3) how to optimize the logic using don't-care conditions. E cient t...