A series of complex logic gates were constructed based on graphene oxide and DNA-templated silver nanoclusters to perform both arithmetic and nonarithmetic functions. For the purpose of satisfying the requirements of progressive computational complexity and cost-effectiveness, a label-free and universal platform was developed by integration of various functions, including half adder, half subtr...

This paper presents anthraquinone and benzimidazole based hybrid molecular architect as the state of the art for multifunctional molecular logic circuits. The moleculator exhibits differential output behavior towards F(-), Zn(2+) and Cu(2+) ions to provide opportunities for elaboration of XOR, INHIBIT, XNOR, AND, OR, NOR, logic functions and their integrated logic functions half-adder, half-sub...

Optical half subtractors are required for designing any optical computation system. Operation speed and the on/off contrast ratios very important characteristics logic device. A novel structure composed of three nonlinear ring resonators some waveguides used proposed subtractor with improved operation ratio. The simulation results show that rise time this is 1.5 ps. Also B D 13.7 dB 14.5 respec...

Floating Point (FP) arithmetic is widely used in large set of scientific and signal processing computation. Adder/subtractor is one of the common arithmetic operation in these computation. The design of FP adder/subtractor is relatively complex than other FP arithmetic operations. This paper has shown an efficient implementation of adder/subtractor module on a reconfigurable platform, which is ...

The capability of multiple valued logic (MVL) circuits to achieve higher storage density when compared that existing binary is highly impressive. Recently, MVL have attracted significant attention for the design digital systems. Carbon nanotube field effect transistors (CNTFETs) shown great promise based circuits, due fact scalable threshold voltage CNTFETs can be utilized easily designs. In ad...

An important arithmetic component of “Arithmetic and Logic Unit” or ALU is reconfigured in this paper, known as “Full-Adder-Subtractor”, where an advance low-power, high-speed nano technology “QCA” with electro-spin criterion used reversibility the advancement multilayer 3D circuitry. In modern digital world, selected nano-sized effective alternative widely “CMOS Technology” because all limitat...

This paper proposes D4 FLMS-GSC algorithm interpreted as Daubechies D4 wavelet filter instead of subtractor filter which processes array antenna output. The structure of the proposed D4 FLMS-GSC algorithm has characteristic of reducing the computational requirement one-half compared to the FLMS-GSC algorithm. In addition, we obtain the MSE characteristics and adaptive beampattern of the D4 FLMS...